Digital Core Design

The Power of Intellectual Property

DoCD - DCD on Chip Debugger

The future is now... Digital Core Design believes in Power of Innovation. Thanks to our revolutionary on-Chip Debugger you can easily become a part of that innovation. The DoCDTM is a complete debugging system, dedicated to DCD's DQ80251/DQ8051/DT8051/DP8051x/DP80390x Microcontroller Cores. The system consists of three major blocks:

DoCDTM provides some serviceable features like a real-time and non-intrusive debug capability, enabling a pre-silicon validation and post-silicon, on chip software debugging. It allows hardware breakpoints, trace, variables watch and multi C sources debugging. The DoCDTM Debug Software can work as a hardware debugger, as well as a software simulator - some tasks can be validated at software simulation level and after this step, you can continue real-time debugging, by uploading code into silicon.

As a DoCDTM user you've got a freedom of choice - you can choose your favorite C compilers or assemblers for software development - it supports most of High Level Object files, produced by C/ASM compiler tools:

Go beyond the limits

System-on-Chip designs are facing the problem of inaccessibility of important control and bus signals, because they often lay behind the physical pins of the device - that makes traditional measurement instrumentation useless. The best way to get around those limitations, is to use on-chip debug tools for the tasks verification and software debuging. Other advantage of an on-chip debugger, is its improved design productivity in an integrated environment, with graphical user's interface. Ability to display/modify memories' content, processor's and peripherals' register windows, along with information tracing and ability to see the related C/ASM source code, are the key elements, that help to improve the design process and thereby, to increase productivity.


Instruction Smart Trace (IST)

The  DoCDTM Hardware Debugger provides debugging capability of a whole System on Chip (SoC). Unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of a running application. It can also efficiently save designer’s time, thanks to hardware trace, called Instructions Smart Trace buffer (IST). The DoCD-IST captures instructions in a smart and non-intrusive way, so it doesn’t capture addresses of all executed instructions, but only these related to the start of tracing, conditional jumps and interrupts. This method does not only save time, but also allows to improve the size of the IST buffer and extend the trace history. Captured instructions are read back by the DoCD-debug software, analyzed and then presented to the user as an ASM code and related C lines.


Perfect service for free

The reason for the developement of the DoCDTM, was to provide our customers with the ability of easy system verification and software debugging, at no additional charges. Therefore, we have decided to add the complete debug system to each 8051/80251/80390 IP Core - for free

Now DCD's customers have the exceptional possibility, to obtain the complete solution for making their own 8051/80251/80390 based, SoC, with the ability to pre-silicon validation and post-silicon software debugging - in one place. It's really unusual opportunity for the designer, to have the ability to get a high quality IP Core and unique on-chip debug tool, from the same supplier.

Debug IP Core

The Debug IP Core is a real-time hardware debugger, which provides an access to all chip registers, memories and peripherals, connected to DCD's IP Core (Dx8051/DQ80251/Dx80390). It controls CPU work, by non-intrusive method. The Debug IP Core is provided as Verilog or VHDL source code, as well as FPGA netlist - depending on the customer requirements. The DoCDTM provides a scaled solution - many SoC designs have both power and area limitations. Debug IP Core, can be scaled to control its gate count. The benefit is fewer gates - for lower use of power and core size, while maintaining excellent debug abilities. Typically, all of the features are utilized in pre-silicon debug (i.e. hardware debugging or FPGA evaluation),  with less features availed in the final silicon

  • Processor execution control
    • Run, Halt
    • Reset
    • Step into instruction
    • Skip instruction
  • Read-write all processor contents
    • Program Counter (PC)
    • Program Memory
    • Internal (direct) Data Memory
    • Special Function Registers (SFRs)
    • External Data Memory
  • Code execution breakpoints
    • up to eight real-time PC breakpoints
    • unlimited number of real-time OPCODE breakpoints
  • Hardware execution watch-points
    • two at Internal (direct) Data Memory
    • two at Special Function Registers (SFRs)
    • two at External Data Memory
  • Hardware watch-points activated at a
    • certain address by any write into memory
    • certain address by any read from memory
    • certain address by write into memory a required data
    • certain address by read from memory a required data
  • Unlimited number of software watch-points
    • Internal (direct) Data Memory
    • Special Function Registers (SFRs)
    • External Data Memory
  • Unlimited number of software breakpoints
    • Program Memory
  • Instructions Smart Trace Buffer – configurable up to 8192 levels (optional)
  • Automatic adjustment of debug data transfer speed rate between HAD2 and Silicon
  • Communication interface
    • TTAG two-wire communication
    • JTAG interface
  • Fully static synchronous design with no internal tri-states

Debug Software

The DoCDTM Software (DS) is a Windows based application. It is fully compatible with all existing 8051/80251/80390 C compilers and Assemblers. The DS was designed to work in two major modes: software simulator mode and hardware debugger mode. Those two modes, allow the pre-silicon software validation in simulation mode and then, real-time debugging of developed software inside silicon - using debugger mode. Once loaded, the program may be observed in Source Window, run at full-speed, single stepped by machine or C-level instructions or stopped at any of the breakpoints. The DoCDTM Debug Software, supports all DCD's 8051/80251/80390 Microcontroller Cores, with their particular configurations:


  • In-system FLASH programming
  • Two working modes
    • hardware debugger
    • software simulator
  • Source Level Debugging:
    • C level hardware/software breakpoints
    • C code execution
      • line by line
      • over line
      • out of function
      • skip line
    • ASM code execution
      • instruction by instruction
      • over instruction
      • out of function
      • skip instruction
    • ASM, C source view of code
  • Symbol Explorer provides hierarchical tree view of all symbols:
    • modules
    • functions
    • blocks
    • variables and more
  • Contents sensitive Watch window
  • Symbolic debug including:
    • code
    • variables
    • variable types
  • Unlimited number of Real-time hardware breakpoints
    • Program Memory (CODE)
  • Two real-time hardware watch-points for each space:
    • Internal (direct) Data Memory (IDM)
    • Special Function Registers (SFR)
    • eXternal Data Memory (XDM)
    • Unlimited number of software breakpoints
      • Program Memory
      • Internal (direct) Data Memory (IDM)
      • Special Function Registers (SFR)
      • eXternal Data Memory (XDM)
    • Set/clear software or hardware breakpoints, watch-points in Disassembled and C Source Code windows
    • 1024 steps deep Software Trace
    • Load Program Memory content from:
      • OMF-51, extended OMF-51 files
      • OMF-251 file
      • Intel HEX-51, HEX-386 files
      • BIN file



  • Auto refresh of all windows, during execution of program
    • Registers panel including ACC, B, PSW, PC, SP, DPTR, DPP and four banks of general purpose registers (R0-R7)
    • Internal (direct) Data Memory (IDM)
    • Special Function Registers (SFR)
    • eXternal Data Memory (XDM)
    • Timers/Counters
    • UARTs
    • I/O Ports
  • Dedicated windows for peripherals
  • Configurable auto refresh time period
  • Status bar containing number of actually executed instructions, number of clock periods and real processor speed rate
  • Hardware Assisted Debugger interface
    • TTAG two-wire interface
    • JTAG interface
  • The system runs on a Windows 2000/2003/XP/7/8/8.1 (both 32 and 64 bits) PC
  • Supports software tools from Keil, Archimedes, IAR, Tasking, Franklin, SDCC and the others

Hardware Assisted Debugger

A high-performance Hardware Assisted Debugger is connected to the target system, containing the DCD's core, either in FPGA or ASIC. HAD2 is a small hardware adapter, that manages communication between the Debug IP Core (JTAG/TTAG/DTAGS protocols) inside silicon and a USB port of the host PC, running DoCDTM Debug Software.

System Features Description


All FLASH memory devices are supported by DoCD debug system. Such support is assured by configurability of FLASH programming algorithm and devices database. New FLASH device, can be easily added to existing base, by using built-in editor. DoCD debugger allows simple in-system programming of its FLASH memory, without using any additional tools. DoCD programming task is performed directly within Debug software and after uploading of the core, it is ready for debugging. Programming time is very short and write operations are performed by certain FLASH device, with maximum speed allowed.


The number of hardware breakpoints is unlimited. Like software breakpoints, hardware execution breakpoints can be set in Program Memory space. They stop program execution just prior an instruction is pointed by Program Counter (PC). In other words, instruction located at the PC breakpoint address, is not executed. The difference is in the method of program execution. In this case, program is run with full clock speed (in real-time) and processor is halted, when hardware signalizes real breakpoint condition.


The number of hardware watch-points is limited to six in different address spaces. Like software breakpoints, hardware execution watch-points can be set in direct RAM, SFRs and external RAM. They stop program execution after an instruction is being executed. The difference is in the method of program execution. In this case, program is run with full clock speed (in real-time) and processor is halted, when hardware signalizes real watch-point condition.


An unlimited number of software breakpoints can be set anywhere in the physical address space of the processor (in Program Memory space, direct RAM, SFRs and external RAM). If at least one software breakpoint is set, program is executed in automatic step by step mode, with checking if certain breakpoint condition is met. Program execution is halted, when breakpoint condition is already met and its execution can be resumed, at any time, in any appro-priate mode.


Mixed breakpoint mode is also allowed and it means that software and hardware breakpoints and watch-points are mixed in the system. This gives you the flexibility in the debugging - for example, two different break conditions can be set, by using watch-points and hardware breakpoints. In each breakpoint mode halt means: CPU is halted and instructions are no longer being fetched and all internal peripherals are also stopped (e.g. timers, watchdog). The UARTs work correctly in any case. 


Symbol Explorer provides hierarchical tree view of all C project symbols. It supports all C types, variables, constants, functions, and symbolic names of registers. Along with watch window, provides flexible and powerful debugging feature at high C language level.


Due tu the fact, that many SoC designs have both power and gate limitations, DCD provides a scaled solution. Debug extensions can be scaled to control gate counts. The benefits are fewer gates, lower power and core size while trading off debug capability.


A Pentium class computer with minimum 512 MB of memory, 32 MB of free space on Hard Disk, CD-ROM drive, USB port and Windows 2000/2003/XP/7/8/8.1 (both 32 and 64 bit) operating system, are required.

TTAG Interface

TTAG version of DoCD Debug IP core symbol and its pins description, are summarized below.


Please note, that TTDI, TTDO, TTDOEN pins are connected together, as single bidirectional pin, called TTDIO.

Pins Description
Pin Type Description
ttdi input DoCDTM data input
ttdo output DoCDTM data output
ttdoen output DoCDTM data output enable
ttck output DoCDTM clock line
Area Utilization
Device vendor Units Area
Altera LC 470
Xilinx Slices 240
Lattice LUT4s 500
ASIC gates 1650

The following table gives a survey about the TTAG versions of Debug IP Core area, in the FPGA and ASIC devices.

JTAG Interface

JTAG version of DoCD Debug IP core symbol and its pins description are summarized below.


Pins Description
Pin Type Description
tdi input DoCDTM TAP data input
tck input DoCDTM TAP clock line
tms input DoCDTM TAP mode select
tdo output DoCDTM TAP data output
rtck output DoCDTM return clock
Area Utilization
Device vendor Units Area
Altera LC 600
Xilinx Slices 300
Lattice LUT4s 610
ASIC gates 2100

The following table gives a survey about the JTAG versions of Debug IP Core area, in the FPGA and ASIC devices.

DoCD in JTAG chain

The DoCDTM debug IP Core v 4.00 and above, can be used as standalone device, as well as plugged into JTAG chain. Standard JTAG pins can be used and other JTAG devices can be controlled, along with DoCD Debug IP. Such solution saves off-chip pins of ASIC/FPGA device.

The example target shown in figure above, consists of DoCD Debug IP and three devices being fully JTAG compliant. The Chip1 has 5-bit long IR (Instruction Register), Chip3 IR's has 3-bit long, and Chip4 has 4-bit long IR. A DR (Data Register) is always 1-bit long for each JTAG device.

The following values should be written into DoCD Windows Debug Software configuration window:

It is shown in figure below.

DTAG Interface

DTAG version of DoCD Debug IP core symbol and its pins description, are summarized below.


Pins Description
Pin Type Description
docddatai input DoCDTM data input
docddatao output DoCDTM data output
docdclk output DoCDTM clock line
Area Utilization
Device vendor Units Area
Altera LC 720
Xilinx Slices 360
Lattice LUT4s 720
ASIC gates 2500

The table above, presents a survey about the DTAG versions of Debug IP Core area, in the FPGA and ASIC devices.