Digital Core Design

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HID Platform

USB 2.0 Human Interface Devices Design Platform

The USB 2.0 HID Design Platform is a complete, integrated solution dedicated to wide range of USB based Human Interface Devices like mouse, keyboard or pen tablet.

The complete HID Design Platform includes:

  • DUSB2 peripheral controller, designed to support 12 Mb/s "Full Speed" (FS) and 480 Mb/s "High Speed" (HS) serial data transmission rates
  • DP8051XP ultra high performance, speed optimized, fully customizable 8051 8-bit microcontroller with built in DoCDTM debug IP core
  • Human Interface Devices software stack optimized for DP8051XP 8-bit CPU
  • FPGA board with ready to use, preprogrammed example HID application
  • HAD2 – DoCDTM Hardware Assisted Debugger board
  • DoCDTM Debug Software
  • DoCDTM driver for Keil development software
  • DoCDTM driver for IAR development software

Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.

Implementation Speed
grade
Utilized Area
 [Slices]
Frequency
 [MHz] 
cpuclk/utmiclk
SC -7 2370 100/>100
ECP2 -7 2570 80/>100
ECP2M -7 2570 70/>100
XP2 -7 2875 60/>100

Implementation results of the USB 2.0 Human Interface Devices Design Platform in LATTICE devices.

Implementation Speed
grade
Utilized Area
[Slices]
Frequency
[MHz]
cpuclk/utmiclk
SPARTAN-III -5 2680 50/>100
SPARTAN-IIIE -5 2680 60/>100
VIRTEX-4 -12 2680 75/>100
VIRTEX-5 -3 1405 90/>100

Implementation results of the USB 2.0 Human Interface Devices Design Platform in XILINX devices.

Implementation Speed
grade
Utilized Area
 [LC]
Frequency
[MHz]
cpuclk/utmiclk
CYCLONE-II -6 4550 60/>100
CYCLONE-III -6 4550 70/>100
STRATIX-II -3 3070 100/>100
STRATIX-III -2 3070 110/>100
Arria GX -6 3070 80/>100

Implementation results of the USB 2.0 Human Interface Devices Design Platform in ALTERA devices.


Key Features

  • Full compliance with the USB 2.0 specification
  • Full-speed 12 Mbps operation
  • High-speed 480 Mbps operation
  • Supports UTMI Transceiver Macrocell Interface
  • Synchronous RAM interface for FIFOs
  • Suspend and resume power management functions
  • 100% software compatible with industry standard 8051
  • Up to 256 bytes of internal (on-chip) Data Memory
  • Up to 64K bytes of internal (on-chip) or external (off-chip) Program Memory
  • Up to 16M bytes of external (off-chip) Data Memory
  • User programmable Program Memory Wait States solution for wide range of memories speed
  • User programmable External Data Memory Wait States solution for wide range of memories speed
  • Allows operation from a wide range of CPU clock frequencies
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking
  • No internal tri-states
  • Lite design, small gate count and fast operation
  • Scan test ready

Applications

  • Keyboard
  • Mouse
  • Pen tablet
  • Trackball
  • Touchpad
  • Joystick
  • Gamepad
  • Steering Wheel
  • Barcode scanner

Symbol

 cpuclk
 prgromdata (7:0)
 prgramdata (7:0)
 ramdatai (7:0)
 sfrdatai (7:0)
 xdatai (7:0)
 int0
 int1
 t0
 gate0
 t1
 gate1
prgaddr (15:0) 
prgdatao (7:0) 
prgramwr 
ramaddr (7:0) 
ramdatao (7:0) 
ramwe 
ramoe 
sfraddr (6:0) 
sfrdatao (7:0) 
sfrwe 
sfroe 
xaddr (23:0) 
xdatao (7:0) 
xdataz 
xprgrd 
xprgwr 
xdatard 
xdatawr 
 utmiclk
 utmilinestate (1:0)
 utmidatai (7:0)
 utmirxvalid
 utmirxactive
 utmirxerror
 utmitxready
utmiopmode (1:0) 
utmidatao (7:0) 
utmitxvalid 
utmisuspendm 
utmixcvrselect 
utmitermselect 
 sramdataia (7:0)
 sramdataib (7:0)
sramaddra (13:0) 
sramaddrb (13:0) 
sramdataoa (7:0) 
sramdataob (7:0) 
sramwea 
sramweb 

Pins description

PinTypeDescription
cpuclkinputCPU clock
prgromdata (7:0)inputData bus from internal ROM program memory
prgramdata (7:0)inputData bus from internal RAM program memory
ramdatai (7:0)inputData bus from internal data memory
sfrdatai (7:0)inputData bus from user SFR"s
xdatai (7:0)inputData bus from external memories
int0inputExternal interrupt 0
int1inputExternal interrupt 1
t0inputTimer 0 input
gate0inputTimer 0 gate input
t1inputTimer 1 input
gate1inputTimer 1 gate input
utmiclkinputUSB clock
utmilinestate (1:0)inputUSB line state
utmidatai (7:0)inputUSB parallel data input bus
utmirxvalidinputUSB receive valid
utmirxactiveinputUSB receive active
utmirxerrorinputUSB receive error
utmitxreadyinputUSB transmit ready
sramdataia (7:0)inputSRAM port A data input bus
sramdataib (7:0)inputSRAM port B data input bus
prgaddr (15:0)outputInternal program memory address bus
prgdatao (7:0)outputData bus for internal program memory
prgramwroutputInternal program memory write
ramaddr (7:0)outputInternal Data Memory address bus
ramdatao (7:0)outputData bus for internal data memory
ramweoutputInternal data memory write enable
ramoeoutputInternal data memory output enable
sfraddr (6:0)outputAddress bus for user SFR"s
sfrdatao (7:0)outputData bus for user SFR"s
sfrweoutputUser SFR"s write enable
sfroeoutputUser SFR"s output enable
xaddr (23:0)outputAddress bus for external memories
xdatao (7:0)outputData bus for external memories
xdatazoutputTurn xdata bus into "Z" state
xprgrdoutputExternal program memory read
xprgwroutputExternal program memory write
xdatardoutputExternal data memory read
xdatawroutputExternal data memory write
utmiopmode (1:0)outputUSB operational mode
utmidatao (7:0)outputUSB parallel data output bus
utmitxvalidoutputUSB transmit valid
utmisuspendmoutputUSB suspend
utmixcvrselectoutputUSB transceiver select
utmitermselectoutputUSB termination select
sramaddra (13:0)outputSRAM port A address bus
sramaddrb (13:0)outputSRAM port B address bus
sramdataoa (7:0)outputSRAM port A data output bus
sramdataob (7:0)outputSRAM port B data output bus
sramweaoutputSRAM port A write enable
sramweboutputSRAM port B write enable

Block Diagram

DP8051XP CPUUltra high performance, speed optimized 8-bit embedded controller, 100% software compatible with industry standard 8051.
cpuclk
prgromdata (7:0)
prgramdata (7:0)
ramdatai (7:0)
sfrdatai (7:0)
xdatai (7:0)
int0
int1
t0
gate0
t1
gate1
prgaddr (15:0)
prgdatao (7:0)
prgramwr
ramaddr (7:0)
ramdatao (7:0)
ramwe
ramoe
sfraddr (6:0)
sfrdatao (7:0)
sfrwe
sfroe
xaddr (23:0)
xdatao (7:0)
xdataz
xprgrd
xprgwr
xdatard
xdatawr
CPU interfaceThe CPU interface module is clocked by cpuclk clock and manages communication with DP8051XP CPU. In this module DUSB2 core configuration and status registers are being located.
UTMI interfaceThe UTMI interface is clocked by utmiclk clock and manages communication with USB 2.0 Transceiver Macrocell. It is responsible for reset detection, speed handshake, token, data and handshake packet reception and transmission.
utmiclk
utmilinestate (1:0)
utmidatai (7:0)
utmirxvalid
utmirxactive
utmirxerror
utmitxready
utmiopmode (1:0)
utmidatao (7:0)
utmitxvalid
utmisuspendm
utmixcvrselect
utmitermselect
SRAM interfaceThe SRAM interface module manages communication with Synchronous Random Access Memory. It generates address, read and write signals for the SRAM memory and buffers data bytes during the FIFO read and write operations.
sramdataia (7:0)
sramdataib (7:0)
sramaddra (13:0)
sramaddrb (13:0)
sramdataoa (7:0)
sramdataob (7:0)
sramwea
sramweb
EP0Special bidirectional endpoint used for device configuration. Allows generic USB control and status access.
EP1Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP2Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

Units

DP8051XP CPU
Ultra high performance, speed optimized 8-bit embedded controller, 100% software compatible with industry standard 8051.
CPU interface
The CPU interface module is clocked by cpuclk clock and manages communication with DP8051XP CPU. In this module DUSB2 core configuration and status registers are being located.
UTMI interface
The UTMI interface is clocked by utmiclk clock and manages communication with USB 2.0 Transceiver Macrocell. It is responsible for reset detection, speed handshake, token, data and handshake packet reception and transmission.

SRAM interface
The SRAM interface module manages communication with Synchronous Random Access Memory. It generates address, read and write signals for the SRAM memory and buffers data bytes during the FIFO read and write operations.
EP0
Special bidirectional endpoint used for device configuration. Allows generic USB control and status access.
EP1
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP2
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.