Digital Core Design

The Power of Intellectual Property

The D68HC08 is an advanced, 8-bit, MCU IP Core, with highly sophisticated, on chip peripheral capabilities. The D68HC08 soft core is binary and cycle-compatible, with the industry standard Motorola 68HC08 8-bit microcontroller. In the standard configuration, the core has integrated on chip major peripheral functions.
The D68HC08 Microcontroller Core, contains full-duplex UART- Asynchronous Serial Communication Interface (SCI) and the Synchronous Serial Peripheral Interface (SPI).
Two 16-bit, flexible timing systems, contain input capture lines, output-compare lines and PWM functionality
Self-monitoring circuitry is included on-chip, to protect against system errors. The Computer Operating Properly (COP) watchdog system, protects against software failures. An illegal opcode detection circuit, provides a non-maskable interrupt, if illegal opcode is detected.
Two software-controlled power-saving modes - WAIT and STOP, are available to conserve additional power. These modes, make the D68HC08 IP Core especially attractive for automotive and battery-driven applications.
D68HC08 is fully customizable - it is delivered in the exact configuration, to meet user's requirements. It includes fully automated testbench with complete set of tests, allowing easy package validation, at each stage of SoC design flow.

Each DCD's D68XX Core, has built-in support for DCD Hardware Debug System, called DoCDTM. It's a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC). Unlike other on-chip debuggers, DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories. More details about DCD on Chip Debugger


Family summary

Family IP Core Architecture
type
Memory space DoCDTM UART (SCI) SPI M/S IO Ports Watchdog
Timer
Timer Compare / Capture Pulse
accumulator
READY
pin
Chip Selects Gatecount
HC05, HC08 DF6805 fast 64k + + - 4 + 1 2/2 - + - 7000
- DF6808 fast 64k + + - 4 + 1 2/2 - + - 8300
- D68HC05 legacy 64k + + + 4 + 1 1/1 - - - -
- D68HC08 legacy 64K + + + 4 + 1 2/1 - - - 10000
HC11 DF6811E fast 64k + + + 5 + 1 5/4 + + - 12000
- DF6811F fast 64k + + + 7 + 1 5/4 + + - 14000
- DF6811K fast 1M + + + 10 + 3 13/6 + + - 21000
- D68HC11E legacy 64k + + + 5 + 1 5/4 + - - 13000
- D68HC11K legacy 1M + + 1 10 + 3 13/6 + - 4 21000
- D68HC11F legacy 64k + + + 7 + 1 5/4 - - 4 13500
6802, 6803 DF6802 fast 64k + - - - - - - - - - -
- DF6803 fast 64k + + + 4 - 1 + - - - -
- D6802 legacy 64k + - - - - - - - - - 3600
- D6803 legacy 64k + + + 4 - 1 + - - - 6000

The main features of each D68XX and DF68XX family member, have been summarized in the table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and request the core modifications.

CPU Features


Symbol

 clk
 rst
 cmf
 docddatai
 clkdocd
docddatao 
docdclk 
 irq
 porta
 portb
 portc
 portd
 porte
 portf
halt 

Pins description

PinTypeDescription
clkinputGlobal clock
rstinputGlobal reset
cmfinputClock monitor fail reset
docddataiinputDoCDTM serial data input
clkdocdinputClock signal to DoCDTM On chip Debugger module. This separate clock line allow DoCDTM to operate during the SLEEP mode (major clock CLK is stopped).
irqinputExternal Interrupt Request
portainputPort A - general-purpose bidirectional I/O Port.
portbinputPort B is a special function port, that in original uC shares all of its port pins with ADC module.
portcinputGenaral-purpose bidirections I/O Port.
portdinputPort D is a special function port, which shares two it"s pins with the timer interface module.
porteinputPort E is a special function bidirectional I/O port,shared with Serial Peripheral Interface (SPI), Timer A (TIMA) a,d Serial Communication Interface (SCI).
portfinputPort F - General purpose bidirectional I./O Port, shared with Timer A and Timer B.
docddataooutputDoCDTM serial data output
docdclkoutputDoCDTM serial data clock line
haltoutputHalt clock system during STOP Instruction

Block Diagram

DoCDTM DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurs at particular address, with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
The separate DoCDTM clock line, allows debugger to operate in the SLEEP mode (major clock line CLK is stopped).
docddatai
docddatao
docdclk
clkdocd
Watchdog TimerThe Watchdog Timer consist of free running timer CLK/213 and control logic. The Watchdog Timer can be enabled by the software, by writing "1" to the WDOG Bit in MISC ($0C) register. Once enabled, the WDT timer cannot be disabled by the software. In addition, the WDOG bit acts as a reset mechanism for the WDT Timer. Writing "1" to the WDOG Bit, clears WDT counter and inhibits Watchdog timeout.
ALUArithmetic Logic Unit performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (A), Condition Code Register (CCREG), Index registers (H:X) and related logic, such as arithmetic unit, logic unit, multiplier and divider.
SPIIt is a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of Serial Clock Signal (SCK). It enables the microcontroller, to communicate with serial peripheral devices. It is also capable of interprocessor communications, in a multi-master system. The Serial Clock Line (SCK) synchronizes shifting and sampling of the information, on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough, to interface directly with numerous standard product peripherals, from several manufacturers. Data rates are as high, as CLK/8. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included, to support interprocessor communications. A write-collision detector indicates, when an attempt is made to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector, automatically disables SPI output drivers, if more than one SPI devices simultaneously attempt to become a bus master.
SCIThe SCI is a full-duplex UART type asynchronous system, using standard, non return to zero (NRZ) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. The Core resynchronizes the receiver bit clock on all one to zero transitions in the bit stream. Therefore, the differences in baud rate, between the sending device and the SCI, are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time and major logic decides the sense for the bit. For the start and stop bits, seven logic samples are taken. Even if noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver also has the ability to enter a temporary standby mode (called receiver wakeup), to ignore messages intended for a different receiver. The logic automatically wakes up the receiver, in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multidrop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual Transmit Data Register Empty (TDRE) status flag, this SCI also provides a Transmit Complete (TC) indication, which can be used in applications with a modem.
BREAK MODULEThe Break Module (BRK) can generate a break interrupt, that stops normal program flow at a defined address, to enter a background program.
Interrupt ControllerExternal Interrupt Controller
irq
I/O PortsAll D68HC08 I/O ports are programmable and can operate as inputs or outputs.
porta
portb
portc
portd
porte
portf
PITProgrammable Interrupt Timer - PIT - is the 16-bit counter, that can operate as a free-running counter or a modulo up-counter. The counter provides the timing reference for the interrupt. The PIT counter modulo registers - PMODH:PMODL, control the modulo value of the counter. Software can read counter value at any time, without affecting the counting sequence.
TIMATimer Interface Module A. The TIMA is a four-channel timer, that provides: a timing reference with input capture, output compare and pulse-width modulation functions.
TIMBTimer Interface Module B. The TIMB is a four-channel timer, that provides: a timing reference with input capture, output compare and pulse-width modulation functions.
Control UnitControl Unit performs the core synchronization and data flow control. This module manages execution of all instructions. The STOP instruction and waking up the processor from the STOP mode.
halt
clk
rst
cmf
Data bus Internal 8-bit data bus.
SFR data bus 8-bit Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture.

Units

DoCDTM
DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurs at particular address, with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
The separate DoCDTM clock line, allows debugger to operate in the SLEEP mode (major clock line CLK is stopped).
Watchdog Timer
The Watchdog Timer consist of free running timer CLK/213 and control logic. The Watchdog Timer can be enabled by the software, by writing "1" to the WDOG Bit in MISC ($0C) register. Once enabled, the WDT timer cannot be disabled by the software. In addition, the WDOG bit acts as a reset mechanism for the WDT Timer. Writing "1" to the WDOG Bit, clears WDT counter and inhibits Watchdog timeout.
ALU
Arithmetic Logic Unit performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (A), Condition Code Register (CCREG), Index registers (H:X) and related logic, such as arithmetic unit, logic unit, multiplier and divider.

SPI
It is a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of Serial Clock Signal (SCK). It enables the microcontroller, to communicate with serial peripheral devices. It is also capable of interprocessor communications, in a multi-master system. The Serial Clock Line (SCK) synchronizes shifting and sampling of the information, on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough, to interface directly with numerous standard product peripherals, from several manufacturers. Data rates are as high, as CLK/8. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included, to support interprocessor communications. A write-collision detector indicates, when an attempt is made to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector, automatically disables SPI output drivers, if more than one SPI devices simultaneously attempt to become a bus master.
SCI
The SCI is a full-duplex UART type asynchronous system, using standard, non return to zero (NRZ) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. The Core resynchronizes the receiver bit clock on all one to zero transitions in the bit stream. Therefore, the differences in baud rate, between the sending device and the SCI, are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time and major logic decides the sense for the bit. For the start and stop bits, seven logic samples are taken. Even if noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver also has the ability to enter a temporary standby mode (called receiver wakeup), to ignore messages intended for a different receiver. The logic automatically wakes up the receiver, in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multidrop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual Transmit Data Register Empty (TDRE) status flag, this SCI also provides a Transmit Complete (TC) indication, which can be used in applications with a modem.
BREAK MODULE
The Break Module (BRK) can generate a break interrupt, that stops normal program flow at a defined address, to enter a background program.

Interrupt Controller
External Interrupt Controller
I/O Ports
All D68HC08 I/O ports are programmable and can operate as inputs or outputs.
PIT
Programmable Interrupt Timer - PIT - is the 16-bit counter, that can operate as a free-running counter or a modulo up-counter. The counter provides the timing reference for the interrupt. The PIT counter modulo registers - PMODH:PMODL, control the modulo value of the counter. Software can read counter value at any time, without affecting the counting sequence.

TIMA
Timer Interface Module A. The TIMA is a four-channel timer, that provides: a timing reference with input capture, output compare and pulse-width modulation functions.
TIMB
Timer Interface Module B. The TIMB is a four-channel timer, that provides: a timing reference with input capture, output compare and pulse-width modulation functions.
Control Unit
Control Unit performs the core synchronization and data flow control. This module manages execution of all instructions. The STOP instruction and waking up the processor from the STOP mode.