Digital Core Design

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DSMART

ISO 7816 based smart card reader

The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications. It provides a communication interface with a smart card, based on ISO 7816-3/EMV4.2 requirements.  DCD’s IP Core implements the hardware support for both T0 character oriented protocol and T1 block oriented protocol. It’s been designed to combine highly reduced CPU utilization and low area consumption, it is able to activate and deactivate cards, perform resets, handle ATR reception and many additional features. Configuration options enable  user to adjust the DSMART to his needs and choose the proprietary options, which will be the most suitable for his design. Data transfer to and from the host system can be interrupt-driven or executed through Direct Memory Access (DMA). The automatic convention detection and decoding mechanism ensure the exact result regardless of the used convention. Elementary Time Unit (ETU) - time duration of the one bit is decoded from the received ATR interface byte and generated automatically. The card clock divider provides non-gated clock with a wide range of possible frequencies. There’s been also a special power down mode implemented, in which the card clock is being hold in two possible states, depending on the card parameter. Error signaling and character repetition are automatic for the T0 protocol. The DSMART incorporates also an optional CRC/LRC hardware checking and generation mechanism which gives the convention independent result. The received CRC/LRC is not stored in the FIFO, but can be read in a case of CRC/LRC error. Also the optional block length counter provides security of the DMA block transfer and automatic CRC/LRC, subjoining with a manual affixing option. The special block mode handles block transfer automatically. Status and error registers provide necessary information about the FIFO state, errors and card events. 

* Note that DSMART works with all major CPUs and is 100% compatible with DCD’s MCUs, enabling the same, cryptography.


Performance

Device Logic Cells Memory Bits Fmax
Aria GX 542 256 147 MHz
Aria 5 394/290 256 366 MHz
Cyclone 784 256 130 MHz
Cyclone 2 783 256 152 MHz
Cyclone 3 775 256 173 MHz
Cyclone 4 778 256 152 MHz
Cyclone 5 362 256 151 MHz
Stratix 771 256 151 MHz
Stratix 2 534/282 256 234 MHz
Stratix 3 532/330 256 349 MHz
Stratix 4 533/330 256 352 MHz
Stratix 5 542/330 256 308 MHz
Stratix GX 771 256 140 MHz
Stratix 2 GX 534/282 256 236 MHz

DSMART implementation results for ALTERA devices.
All features have been included.
 

Device Slices/Luts Memory Blocks Fmax
Artix 7 207/495 2 260 MHz
Zynq 224/512 2 318 MHz
Spartan 3 452/666 2 86 MHz
Spartan 3E 457/669 2 91 MHz
Spartan 6 284/495 2 143 MHz
Virtex 4 486/728 2 200 MHz
Virtex 5 243/558 2 221 MHz
Virtex 6 205/457 2 245 MHz
Kintex 7 218/500 2 280 MHz

DSMART implementation results for Xilinx devices.
All features have been included.
 

Device Slices/Luts Memory Bits Fmax
ECP 368/592 256 74 MHz
ECP2 383/597 256 84 MHz
ECP2M 383/597 256 84 MHz
ECP3 383/600 256 84 MHz
XP 368/592 256 52 MHz
XP2 381/594 256 67 MHz
SC 406/639 256 131 MHz
SCM 405/638 256 118 MHz

DSMART implementation results for Lattice devices.
All features have been included.
 


Key Features

  • Compatible with the ISO 7816-3: 2006 and EMV 4.1 standard
  • Support for asynchronous Smart Cards
  • Dual configurable length FIFO with two programmable thresholds
  • Card detection input
  • Software-configurable interrupts
  • Automatic convention detection and decoding
  • Programmable non-gated card clock generator
  • Automatic ETU generator
  • DMA support for transmit and receive
  • Hardware CRC and LRC calculations
  • Card power down mode with clock stop high and clock stop low possibility
  • Special fast block mode for T1 protocol (optional)
  • CRC/LRC hardware generation and checking
  • Byte counter with automatic CRC/LRC affixing(optional)
  • No inertial tri-state buffers
  • Fully synchronous synthesizable design
     

Applications

  • General purpose smart card readers
  • SO-7816 / EMV Bridges
  • Personal Wireless devices & SIM Readers in Telecom
  • Payphones and vending machines
  • Personal identification
  • Satellite TV security
  • Health care records storage

Symbol

 rst
 clk
 addr (3:0)
 datai (7:0)
 rd
 wr
 cs
datao (7:0) 
int 
dataen 
rw 
c5V3 
c18 
 seriali
serialo 
 ackr
 ackt
reqr 
reqt 
 cdet
cclk 
crst 
cvcc_en 

Pins description

PinTypeDescription
rstinputGlobal reset
clkinputGlobal clock
addr (3:0)inputAddress bus
datai (7:0)inputParallel data input
rdinputRead input
wrinputWrite input
csinputChip select input
serialiinputSerial Data Input
ackrinputReceiver DMA acknowledge signal
acktinputTransmiter DMA acknowledge signal
cdetinputCard detection
datao (7:0)outputParallel data output
intoutputInterrupt request output
dataenoutputTri-state buffer controll of pallalel data buses
rwoutputTri-state buffer control pin
c5V3outputSwitch between A and B class of operation
c18outputC class operating voltage detection
serialooutputSerial Data Output
reqroutputReceiver DMA request signal
reqtoutputTransmiter DMA request signal
cclkoutputCard clock
crstoutputCard reset
cvcc_enoutputSmard card voltage enable

Block Diagram

Interface Responsible for a communication with the CPU unit. Contains registers which inform about the status and control the DSMART actions. Access to the registers is through the address strobe(ADDR[4:0]) and the data strobe(DATAI[7:0], DATAO[7:0]). To control the read and write process the write(wr) and read(rd) pins are used. Both are active high. The active low Chip select(CS) signal is used to enable or disable data interface.
rst
clk
addr (3:0)
datai (7:0)
datao (7:0)
rd
wr
cs
int
dataen
rw
c5V3
c18
RX_FIFOThe FIFO width is configurable. It has four trigger levels which can be the source of the interrupt or DMA requests. Two of them can be set before synthesis process. The receiver FIFO will continue to store bytes, until it is full and will not accept any more bytes. The DSMART has protection which prevents from the unwanted random read.
TX_FIFOThe FIFO width is configurable. It has four trigger levels which can be the source of the interrupt or DMA requests. Two of them can be set before synthesis process. The receiver FIFO will continue to store bytes, until it is full and will not accept any more bytes. The DSMART has protection which prevents from the unwanted random write.
CRC and LRC Hardware GeneratorIt either checks the CRC\LRC of the incoming bytes or generates and append it to the message. This process can be full automate or CPU controlled. The CRC is checked against polynomial and LRC is XOR of all bytes in the message.
ISO 7816-3 UARTIn general it is responsible for transmitting and receiving data according to the ISO standard. It automatically generates appropriate transmission clock(ETU) and preserve all timing requirements.
seriali
serialo
DMA module The direct memory access module allows to transfer data to and from target memory without the CPU intervention. Both acknowledge and request signals are active high.
reqr
ackr
reqt
ackt
Block ModuleSpecial improvement for block oriented T1 protocol. It allows to manage the block transfer much more effectively with smaller CPU resources consumption. This solution will give effects using the Direct Memory Access and CRC/LRC Hardware Generator.
CARD_CONTROL MODULEThis module manages activation, deactivation, reset and clock stop. All timing requirements are automatically preserved.
cclk
crst
cvcc_en
cdet
Internal data bus 8-bit internal data bus

Units

Interface
Responsible for a communication with the CPU unit. Contains registers which inform about the status and control the DSMART actions. Access to the registers is through the address strobe(ADDR[4:0]) and the data strobe(DATAI[7:0], DATAO[7:0]). To control the read and write process the write(wr) and read(rd) pins are used. Both are active high. The active low Chip select(CS) signal is used to enable or disable data interface.
RX_FIFO
The FIFO width is configurable. It has four trigger levels which can be the source of the interrupt or DMA requests. Two of them can be set before synthesis process. The receiver FIFO will continue to store bytes, until it is full and will not accept any more bytes. The DSMART has protection which prevents from the unwanted random read.
TX_FIFO
The FIFO width is configurable. It has four trigger levels which can be the source of the interrupt or DMA requests. Two of them can be set before synthesis process. The receiver FIFO will continue to store bytes, until it is full and will not accept any more bytes. The DSMART has protection which prevents from the unwanted random write.

CRC and LRC Hardware Generator
It either checks the CRC\LRC of the incoming bytes or generates and append it to the message. This process can be full automate or CPU controlled. The CRC is checked against polynomial and LRC is XOR of all bytes in the message.
ISO 7816-3 UART
In general it is responsible for transmitting and receiving data according to the ISO standard. It automatically generates appropriate transmission clock(ETU) and preserve all timing requirements.
DMA module
The direct memory access module allows to transfer data to and from target memory without the CPU intervention. Both acknowledge and request signals are active high.

Block Module
Special improvement for block oriented T1 protocol. It allows to manage the block transfer much more effectively with smaller CPU resources consumption. This solution will give effects using the Direct Memory Access and CRC/LRC Hardware Generator.
CARD_CONTROL MODULE
This module manages activation, deactivation, reset and clock stop. All timing requirements are automatically preserved.