Digital Core Design

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D85C30

UART Core with SDLC Function

    UART IP Core with SDLC Function

    The D85C30 - (Serial Communication Controller) is a dual channel USART (Universal Synchronous/Asynchronous Receiver/Transmitter) device, designed for use with 8 and 16-bit microprocessors. It functions as serial-to-parallel, parallel-to-serial converter/controller and can be software-configured to satisfy a wide variety of serial communications applications. The device contains a variety of new, sophisticated internal functions, including on-chip baud rate generators. The D85C30 handles asynchronous formats, synchronous byte-oriented protocols, such as IBM® Bisync, and synchronous bit-oriented protocols, like HDLC and IBM SDLC. This versatile device supports virtually any serial data transfer application (telecommunication, LAN, etc.). The device can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The D85C30 has also facilities for modem control in both channels. In applications where these controls are not needed, modem controls can be used for general-purpose I/O. The D85C30 can be configured by user to handle all synchronous formats, regardless of data size, number of stop bits or parity requirements. The D85C30 is controlled through access to 14 Write registers and 7 Read registers per channel (the number of the registers varies depending on the version). Within each operating mode, the D85C30 also allows for protocol variations by checking odd or even parity bits, character insertion or deletion, CRC generation, checking break and abort generation and detection, and many other protocol-dependent features.


    Family summary

    UART Feature DμART D2692 D16450 D16550 D16750 D16552 D16752 D16950 D85C30
    FIFO Size - 2*8 - 2*16 2*64 4*16 x*2*64 2*128 4
    Multichannel option - - - - - + + - -
    Separate BAUD Clock line + - + + + + + + +
    Modem Control - - + + + + + + +
    False Start Bit detection + + + + + + + + +
    Status report + + + + + + + + +
    Internal diagnostic capabilities + + + + + + + + +
    Prioritized interrupt system - + + + + + + + +
    Break generation and detection - + + + + + + + +
    Fast mode CLK/4 - - - - o - o + -
    Half-Duplex RS485 - + - - o - o + +
    RS485 buffer enable - - - + + - + + +
    IRDA support - - - - o + - + -
    Additional CLK prescaler - - - - - - + - -
    1284 Parallel Port - - - - - + - - -
    Hardware flow control RTS/CTS - + - - + - + + +
    Software flow control Xon/Xoff - - - - - - + + -
    Isochronous mode - - - - - - - + +
    Detector of bad data in receiver FIFO - + - + + + + + +
    Special character detection - - - - - - + + -
    Software channel reset - - - - - - - + -
    4 byte device ID - - - - - - - + -
    Trigger levels for receiver and transmitter - - - - - - - + -
    Hardware flow control DTS/DTR - - - - - - - + -
    Optional FIFO size extension to 512 bytes - - - - + - + - -

    The main features of each UART family member have been summarized in table above. It gives a briefly member characterization helping you to select the most suitable IP Core for your application.

    Performance

    D85C30 has been tested in variety of FPGA and ASIC technologies.

    Implementation Logic Cells MEMORY
    Bits
    Frequency [MHz]
    ARIA 2033/943 608 83
    ARIA II 1954/943 608 167
    ARIA V 1966/1052 608 118
    CYCLONE 2730 608 68
    CYCLONE II 2883 608 90
    CYCLONE III 2896 608 109
    CYCLONE IV E 2869 608 112
    CYCLONE IV 6X 2881 608 112
    CYCLONE V 1967 608 89
    STRATIX 2730 608 72
    STRATIX II 2037 608 123
    STRATIX III 1962/997 608 214
    STRATIX IV 1952/997 608 196
    STRATIX V 1950/1044 608 219

    D85C30 implementation results for ALTERA devices.
    All features have been included.

    Implementation LUTs/Slices MEMORY
    Blocks
    Frequency [MHz]
    Artix 7 1785/797 2 165
    Kintex 7 1877/676 2 239
    Zynq 1868/774 2 171
    Virtex 7 1869/878 2 194
    Virtex 6 1801/850 2 144
    Virtex 5 1861/846 2 161
    Virtex 4 2533/1598 2 121
    Spartan 6 1815/681 2 122
    Spartan 3E 2647/1655 2 75
    Spartan 3 2625/1645 2 72

    D85C30 implementation results for XILINX devices.
    All features have been included.


    Key Features

    • Software compatible with Z85C30
    • Dual Channel: A, B
    • Configuration capability
    • Asynchronous mode:
      • Asynchronous (x16, x32, or x64 clock
      • Isochronous (x1 clock)
    • Character-Oriented mode:
      • Monosynchronous
      • Bisynchronous
      • External Synchronous
    • Bit-Oriented mode:
      • SDLC/HDLC
      • SDLC/HDLC Loop
    • Complete status reporting capabilities
    • Receiver data FIFO and Error FIFO
    • SDLC Frame FIFO
    • Data encoder\decoder:
      • NRZ, NRZI
      • FM0, FM1
      • Manchester (require external logic)
    • Line break generation and detection
    • Internal diagnostic capabilities:
      • Loop-back controls for communications link fault isolation
      • Auto Echo
      • Break, parity, overrun, framing error simulation
    • Fully synchronous design with no internal tristate buffers

    Applications

    • Serial Data communications applications
    • Modem interface
    • Embedded microprocessor boards

    Symbol

     rxd (a,b)
     rtxc (a, b)
     trxci (a,b)
    txd (a, b) 
    trxco (a,b) 
    trxcen (a,b) 
     clk
     rst
     PCLK
     PCLKEN
     addr (3:0)
     directaddr
     datai (7:0)
     rd
     wr
     cs
     ab
     dc
    datao (7:0) 
    dataen 
    wreq (a, b) 
     cts (a, b)
     dcd (a, b)
     synci (a, b)
    rts (a, b) 
    dtrreq (a, b) 
    synco (a, b) 
    syncen (a, b) 
     intack
     iei
    int 
    ieo 

    Pins description

    PinTypeDescription
    rxd (a,b)inputSerial data input
    rtxc (a, b) inputRTXC Clock input
    trxci (a,b)inputTRXC Clock input
    clkinputGlobal clock
    rstinputGlobal reset
    PCLKinputBaud generator clock
    PCLKENinputBaud generator clock enable - 1 enable the PCLK
    addr (3:0)inputAddress Bus
    directaddrinputConfiguration pin, when high enable the address bus
    datai (7:0)inputParallel Data input
    rdinputRead input
    wrinputWrite input
    csinputChip select input
    abinputChannel A/Channel B input
    dcinputData/Command
    cts (a, b)inputClear to send input
    dcd (a, b)inputData carrier detect input
    synci (a, b)inputSYNC Pin input
    intackinputInterrupt acknowledge
    ieiinputInterrupt enable input
    txd (a, b)outputSerial data output
    trxco (a,b)outputTRXC Clock output
    trxcen (a,b)outputTRXC Clock output enable
    datao (7:0)outputParallel data output
    dataenoutputParallel data output enable
    wreq (a, b)outputWAIT Request
    rts (a, b)outputRequest To Send pin
    dtrreq (a, b)outputData Terminal Rready Request
    synco (a, b)outputSYNC Pin output
    syncen (a, b)outputSYNC Buffer output enable
    intoutputInterrupt request
    ieooutputInterrupt enable output

    Block Diagram

    RCVR Buffer and RCVR FIFO
    Receiver Control and Shift Register
    rxd (a,b)
    rtxc (a, b)
    TX Buffer
    Transmitter Control and Shift Register
    txd (a, b)
    trxci (a,b)
    trxco (a,b)
    trxcen (a,b)
    Baud Generator
    clk
    rst
    PCLK
    PCLKEN
    Data Bus Buffer
    addr (3:0)
    directaddr
    datai (7:0)
    datao (7:0)
    dataen
    rd
    wr
    cs
    ab
    dc
    wreq (a, b)
    Modem Control Logic
    rts (a, b)
    cts (a, b)
    dtrreq (a, b)
    dcd (a, b)
    synci (a, b)
    synco (a, b)
    syncen (a, b)
    Interrupt Controller
    int
    intack
    iei
    ieo
    Internal data bus 8-bit internal data bus

    Units

    RCVR Buffer and RCVR FIFO
    Receiver Control and Shift Register
    TX Buffer

    Transmitter Control and Shift Register
    Baud Generator
    Data Bus Buffer

    Modem Control Logic
    Interrupt Controller