Digital Core Design

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DRPIC1655X

x4 - High Performance 8-bit RISC Microcontroller

The DRPIC1655X is a low-cost, high performance, 8-bit, fully static soft IP Core, intended to operate with fast, dual ported memory. The core has been designed with a special concern about low power consumption, assuring the best power use, price and performance combination available on the IP cores market.
The DRPIC1655X soft core is software-compatible with the industry standard PIC 16XXX Microcontrollers. It implements an enhanced Harvard architecture (separate instruction and data memories), with independent address and data buses. The 14 bit program memory and 8-bit dual port data memory allow instruction fetch and data operations, to occur simultaneously. The advantage of this architecture, is that instruction fetch and memory transfers can be overlapped by multi stage pipeline, so that the next instruction can be fetched from program memory, while the current instruction is executed with data, from the data memory. The DRPIC1655X architecture is 4 times faster compared to standard architecture. Most instructions are executed within 1 system clock period, except the instructions, which operate directly on PC (GOTO, CALL, RETURN) program counter. This situation requires the pipeline to be cleared and subsequently refilled. This operation takes additional one clock cycle.
The DRPIC1655X Microcontroller perfectly fits in applications ranging from high-speed automotive and appliance motor control, to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode makes this IP core perfect for applications, where the power consumption aspect is critical.
The DRPIC165X is delivered with fully automated testbench, complete set of tests and DoCD TM on-chip hardware debugger,  allowing easy package validation, at each stage of SoC design flow.

Each of the DCD's PIC Core, has built-in support for the DCD Hardware Debug System called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).

Unlike other on-chip debuggers, DoCDTM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories. More details about DCD on Chip Debugger


Family summary

Design Architecture improvement Code space DATA space Program word Number of instructions I/O Ports Timers Watchdog Timer CCP1 USART SLEEP Mode DoCD TM Size (gates)
DFPIC165X 2 2k 128 12 bit 33 24 1 + - - + - 2700
DFPIC1655X 2 64k 32 kB 14 bit 35 16 1 + - - + + 3900
DFPIC166X 2 64k 32 kB 14 bit 35 32 3 + 1 1 + + 5800
DRPIC1655X 4 64k 32 kB 14 bit 35 32 1 + - - + + 4800
DRPIC166X 4 64k 32 kB 14 bit 35 32 3 + 1 1 + + 6700

The main features of each PIC family member have been summarized in table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and requests the core modifications.

Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

Implementation Speed
grade
Utilized Area
[LUT/PFU]
Frequency
[MHz]
EC -5 1060/307 85
ECP -5 1060/307 85
XP -5 1060/307 78

Implementation results for LATTICE devices.

Implementation Speed
grade
Utilized Area
[Slices]
Frequency
[MHz]
SPARTAN-IIE -7 473 47
SPARTAN-III -5 483 59
SPARTAN-IIIE -4 489 45
VIRTEX-E -8 474 51
VIRTEX-II -6 484 86
VIRTEX-II pro -7 483 102
VIRTEX-IV -12 483 109

Implementation results for XILINX devices.


Implementation Speed
grade
Utilized Area
[LC]
Frequency
[MHz]
APEX20KC -7 1131 81
CYCLONE -6 921 111
CYCLONE II -6 923 107
STRATIX -5 922 114
STRATIX II -3 823 189
STRATIX GX -5 922 116

Implementation results for ALTERA devices.

Implementation Speed
grade
Utilized Area
[TILES]
Frequency
[MHz]
FUSION -2 1803 47
ProASIC3 -2 1968 49
ProASIC3e -2 1803 47
IGLOO STD 1968 25
IGLOOe STD 1803 25

Implementation results for ACTEL devices.


CPU Features


Symbol

 clk
 por
 mclr
 prgdata (13:0)
sleep 
prgaddr (15:0) 
 portai (7:0)
 portbi (7:0)
 portci (7:0)
 portdi (7:0)
portao (7:0) 
portbo (7:0) 
portco (7:0) 
portdo (7:0) 
trisa (7:0) 
trisb (7:0) 
trisc (7:0) 
trisd (7:0) 
 int
 ramdatai (7:0)
ramdatao (7:0) 
rdaddr (8:0) 
ramwe 
ramoe 
wraddr (8:0) 
 t0cki
 clkwdt
 docddatai
docddatao 
docdclk 
prgdatao (13:0) 
prgwe 

Pins description

PinTypeDescription
clkinputGlobal clock
porinputGlobal reset Power On Reset
mclrinputUser reset
prgdata (13:0)inputData bus from program memory
portai (7:0)inputPort A input
portbi (7:0)inputPort B input
portci (7:0)inputPort C input
portdi (7:0)inputPort D input
intinputExternal interrupt
ramdatai (7:0)inputData bus from int. data memory
t0ckiinputTimer 0 input
clkwdtinputWatchdog clock
docddataiinputDoCDTM data input
sleepoutputSleep signal
prgaddr (15:0)outputProgram memory address bus
portao (7:0)outputPort A output
portbo (7:0)outputPort B output
portco (7:0)outputPort C output
portdo (7:0)outputPort D output
trisa (7:0)outputData direction pins for Port A
trisb (7:0)outputData direction pins for Port B
trisc (7:0)outputData direction pins for Port C
trisd (7:0)outputData direction pins for Port D
ramdatao (7:0)outputData bus for internal data memory
rdaddr (8:0)outputRAM read address bus
ramweoutputData memory write
ramoeoutputData memory output enable
wraddr (8:0)outputRAM write address
docddataooutputDoCDTM data output
docdclkoutputDoCDTM clock line
prgdatao (13:0)outputProgram memory data bus output
prgweoutputProgram memory write enable

Block Diagram

Control UnitIt performs the core synchronization and data flow control. This module manages execution of all instructions. It carries out the decode and control functions for all other blocks. It contains program counter (PC) and hardware stack.
mclr
sleep
prgdata (13:0)
prgaddr (15:0)
Hardware StackIt's a configurable hardware stack. The stack space is not a part of either program or data space and the stack pointer is neither readable, nor writable. The PC is pushed onto the stack, when CALL instruction is executed or an interrupt causes a branch. The stack is popped, while RETURN, RETFIE and RETLW instruction is executed. The stack operates, as a circular buffer - this means, that after the stack has been pushed eight times, the ninth push overwrites the value, that was stored from the first push.
I/O PortsThe ports block contains general purpose I/O ports and data direction registers (TRIS). The DRPIC16XXX has four 8-bit full bi-directional ports PORT A, PORT B, PORT C, PORT D. Each port's bit can be individually accessed, by bit addressable instructions. Read and write accesses to the I/O port, are performed via their corresponding SFR's PORTA, PORTB, PORTC, PORTD. The reading instruction, always reads the status of Port pins. Writing instructions always write into the Port latches. Each port's pin has an corresponding bit in TRISA, B, C and D registers. When the bit of TRIS register is set, it means, that the corresponding bit of port is configured as an input (output drivers are set into the High Impedance).
portai (7:0)
portbi (7:0)
portci (7:0)
portdi (7:0)
portao (7:0)
portbo (7:0)
portco (7:0)
portdo (7:0)
trisa (7:0)
trisb (7:0)
trisc (7:0)
trisd (7:0)
Interrupt ControllerInterrupt Controller module is responsible for interrupt manage system for the external and internal interrupt sources. It contains interrupt related register, called INTCON. There are three interrupt sources:
  • External interrupt INT
  • TMR0 overflow interrupt
  • PORTB change interrupt (pins B[7:4])
INTCON records individual interrupt requests in flag bits. A global interrupt enable (GIE) bit enables all unmasked interrupts. Each interrupt source, has an individual enable bit, which can enable or disable corresponding interrupt. When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. The interrupt flag bits must be cleared in software before re-enabling interrupts.
int
ALUArithmetic Logic Unit - performs arithmetic and logic operations during execution of an instruction. This module contains work register (W) and Status register.
RAM ControllerIt performs interface functions between Data Memory and DRPIC16XXX internal logic. It assures correct Data Memory addressing and data transfers. The DRPIC16XXX supports two addressing modes: direct or indirect. In Direct Addressing, the 9-bit direct address is computed from RP(1:0) bits (STATUS) and from 7 least significant bits of instruction word. Indirect addressing is possible, by using the INDF register. Any instruction using INDF register, actually accesses data pointed to by the FSR (file select register). Reading INDF register indirectly, will produce 00h. Writing to the INDF register indirectly, results in a nooperation. An effective 9-bit address is obtained, by concatenating the IRP bit (STATUS) and the 8-bit FSR register.
ramdatai (7:0)
ramdatao (7:0)
rdaddr (8:0)
ramwe
ramoe
wraddr (8:0)
Timer 0Main system's timer and prescaler. It operates in two modes: 8-bit timer or 8-bit counter. In the \"timer mode\", timer/prescaler registers are incremented in every instruction cycle (1 or 2 CLK periods). When the prescaler is assigned into the TIMER, prescaler ratio can be divided by 2, 4, ..., 256. In the \"counter mode\", the timer register is incremented in every falling or rising edge of T0CKI pin, depending on T0SE bit in OPTION register.
t0cki
Watchdog TimerThe watchdog timer is a free running timer. WDT has its own clock input, separate from system clock. It means, that the WDT will run, even if the system clock is stopped by execution of SLEEP instruction. During normal operation, a WDT timeout generates a Watchdog reset. If the device is in SLEEP mode, the WDT timeout causes the device to wake-up and continue with normal operation.
clkwdt
DoCDTM DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurred at particular address, with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools, to communicate and work with core, in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
docddatai
docddatao
docdclk
prgdatao (13:0)
prgwe
clk
por
Data bus The core internal data bus

Units

Control Unit
It performs the core synchronization and data flow control. This module manages execution of all instructions. It carries out the decode and control functions for all other blocks. It contains program counter (PC) and hardware stack.
Hardware Stack
It's a configurable hardware stack. The stack space is not a part of either program or data space and the stack pointer is neither readable, nor writable. The PC is pushed onto the stack, when CALL instruction is executed or an interrupt causes a branch. The stack is popped, while RETURN, RETFIE and RETLW instruction is executed. The stack operates, as a circular buffer - this means, that after the stack has been pushed eight times, the ninth push overwrites the value, that was stored from the first push.
I/O Ports
The ports block contains general purpose I/O ports and data direction registers (TRIS). The DRPIC16XXX has four 8-bit full bi-directional ports PORT A, PORT B, PORT C, PORT D. Each port's bit can be individually accessed, by bit addressable instructions. Read and write accesses to the I/O port, are performed via their corresponding SFR's PORTA, PORTB, PORTC, PORTD. The reading instruction, always reads the status of Port pins. Writing instructions always write into the Port latches. Each port's pin has an corresponding bit in TRISA, B, C and D registers. When the bit of TRIS register is set, it means, that the corresponding bit of port is configured as an input (output drivers are set into the High Impedance).

Interrupt Controller
Interrupt Controller module is responsible for interrupt manage system for the external and internal interrupt sources. It contains interrupt related register, called INTCON. There are three interrupt sources:
  • External interrupt INT
  • TMR0 overflow interrupt
  • PORTB change interrupt (pins B[7:4])
INTCON records individual interrupt requests in flag bits. A global interrupt enable (GIE) bit enables all unmasked interrupts. Each interrupt source, has an individual enable bit, which can enable or disable corresponding interrupt. When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. The interrupt flag bits must be cleared in software before re-enabling interrupts.
ALU
Arithmetic Logic Unit - performs arithmetic and logic operations during execution of an instruction. This module contains work register (W) and Status register.
RAM Controller
It performs interface functions between Data Memory and DRPIC16XXX internal logic. It assures correct Data Memory addressing and data transfers. The DRPIC16XXX supports two addressing modes: direct or indirect. In Direct Addressing, the 9-bit direct address is computed from RP(1:0) bits (STATUS) and from 7 least significant bits of instruction word. Indirect addressing is possible, by using the INDF register. Any instruction using INDF register, actually accesses data pointed to by the FSR (file select register). Reading INDF register indirectly, will produce 00h. Writing to the INDF register indirectly, results in a nooperation. An effective 9-bit address is obtained, by concatenating the IRP bit (STATUS) and the 8-bit FSR register.

Timer 0
Main system's timer and prescaler. It operates in two modes: 8-bit timer or 8-bit counter. In the \"timer mode\", timer/prescaler registers are incremented in every instruction cycle (1 or 2 CLK periods). When the prescaler is assigned into the TIMER, prescaler ratio can be divided by 2, 4, ..., 256. In the \"counter mode\", the timer register is incremented in every falling or rising edge of T0CKI pin, depending on T0SE bit in OPTION register.
Watchdog Timer
The watchdog timer is a free running timer. WDT has its own clock input, separate from system clock. It means, that the WDT will run, even if the system clock is stopped by execution of SLEEP instruction. During normal operation, a WDT timeout generates a Watchdog reset. If the device is in SLEEP mode, the WDT timeout causes the device to wake-up and continue with normal operation.
DoCDTM
DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurred at particular address, with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools, to communicate and work with core, in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.