Digital Core Design

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DFPIC165X

x2 - 8-bit RISC Microcontroller

The DFPIC165X is a low-cost, high performance, 8-bit, fully static soft IP Core, intended to operate with fast memory (typically on-chip). The core has been designed with a special concern about low power consumption.
The DFPIC165X software is compatible with the PIC16C54, PIC16C55, PIC16C56, PIC16C57 and PIC16C58 industry standards. It has a modified RISC architecture (2 times faster than original implementation).
The DFPIC165X has enhanced core features and configurable hardware stack. The separate instruction and data buses allow a 12 bit wide instruction word, with the separate 8-bit wide data. The DFPIC165X typically achieves a 2:1 code compression and a 8:1 speed improvement, over other 8-bit microcontrollers in its class. The Core has 24 I/O lines and an 8-bit timer/counter, with an 8-bit programmable prescaller.
The power-down SLEEP mode allows user, to reduce power consumption. User can "wake up" the controller from SLEEP, through an user reset or watchdog overflow. An integrated Watchdog Timer (with it's own clock signal) provides protection against software lock-up.
The DFPIC165X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control, to low-power, remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode and small used area in programmable devices, make this IP core perfect for applications with space and power consumption limitations.
The DFPIC165X is delivered with fully automated testbench and complete set of tests, allowing easy package validation, at each stage of SoC design flow.


Family summary

Design Architecture improvement Code space DATA space Program word Number of instructions I/O Ports Timers Watchdog Timer CCP1 USART SLEEP Mode DoCD TM Size (gates)
DFPIC165X 2 2k 128 12 bit 33 24 1 + - - + - 2700
DFPIC1655X 2 64k 32 kB 14 bit 35 16 1 + - - + + 3900
DFPIC166X 2 64k 32 kB 14 bit 35 32 3 + 1 1 + + 5800
DRPIC1655X 4 64k 32 kB 14 bit 35 32 1 + - - + + 4800
DRPIC166X 4 64k 32 kB 14 bit 35 32 3 + 1 1 + + 6700

The main features of each PIC family member have been summarized in table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and requests the core modifications.

CPU Features


Symbol

 clk
 por
 mclr
 prgdata (11:0)
sleep 
prgaddr (11:0) 
 portai (7:0)
 portbi (7:0)
 portci (7:0)
portao (7:0) 
portbo (7:0) 
portco (7:0) 
trisa (7:0) 
trisb (7:0) 
trisc (7:0) 
 ramdatai (7:0)
ramdatao (7:0) 
ramaddr (7:0) 
ramwe 
ramoe 
 t0cki
 clkwdt

Pins description

PinTypeDescription
clkinputGlobal clock
porinputGlobal reset Power On Reset
mclrinputUser reset
prgdata (11:0)inputData bus from program memory
portai (7:0)inputPort A input
portbi (7:0)inputPort B input
portci (7:0)inputPort C input
ramdatai (7:0)inputData bus from int. data memory
t0ckiinputTimer 0 input
clkwdtinputWatchdog clock
sleepoutputSleep signal
prgaddr (11:0)outputProgram memory address bus
portao (7:0)outputPort A output
portbo (7:0)outputPort B output
portco (7:0)outputPort C output
trisa (7:0)outputData direction pins for Port A
trisb (7:0)outputData direction pins for Port B
trisc (7:0)outputData direction pins for Port C
ramdatao (7:0)outputData bus for internal data memory
ramaddr (7:0)outputRAM address bus
ramweoutputData memory write
ramoeoutputData memory output enable

Block Diagram

Hardware stackThe DFPIC165X configurable hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is pushed onto the stack when CALL instruction is executed or an interrupt causes a branch. The stack is popped while RETLW instruction is executed. The stack operates as a circular buffer - after the stack has been pushed two times, the third push overwrites the value, which was stored from the first push.
Control UnitIt performs the core synchronization and data flow control. This module manages execution of all instructions. Performs decode and control functions for all other blocks. It contains program counter (PC) and hardware stack.
mclr
sleep
prgdata (11:0)
prgaddr (11:0)
ALUArithmetic Logic Unit - performs arithmetic and logic operations during execution of an instruction. This module contains work register (W) and Status register.
I/O PortsI/O ports block contains DFPIC165X's general purpose I/O ports and data direction registers (TRIS). The DRPIC165X has three 8-bit full bi-directional ports PORT A, PORT B and PORT C. Read and write accesses to the I/O port are performed via their corresponding SFR's PORTA, PORTB, PORTC. The reading instruction always reads the status of Port pins. Writing instructions always write into the Port latches. Each port's pin has an corresponding bit in TRISA, TRISB and TRISC registers. When the bit of TRIS register is set, it means, that the corresponding bit of port is configured as an input (output drivers are set into the High Impedance).
portai (7:0)
portbi (7:0)
portci (7:0)
portao (7:0)
portbo (7:0)
portco (7:0)
trisa (7:0)
trisb (7:0)
trisc (7:0)
RAM ControllerIt performs interface functions between Data memory and DFPIC165X internal logic. It assures correct Data memory addressing and data transfers. The DFPIC165X supports two addressing modes: direct or indirect. In Direct Addressing, the 8-bit direct address is computed from FSR(7:5) bits and from 5 least significant bits of instruction word. Indirect addressing is possible, by using the INDF register. Any instruction using INDF register, actually accesses data pointed to by FSR (file select register). Reading INDF register indirectly, will produce 00h. Writing to the INDF register indirectly, results in a no-operation. An effective 8-bit address is obtained from an 8-bit FSR register.
ramdatai (7:0)
ramdatao (7:0)
ramaddr (7:0)
ramwe
ramoe
Timer 0Main system's timer and prescaler. It operates in two modes: 8-bit timer or 8-bit counter. In the \"timer mode\", timer/prescaler registers are incremented in every instruction cycle (1 or 2 CLK periods). When the prescaler is assigned into the TIMER, prescaler ratio can be divided by 2, 4, ..., 256. In the \"counter mode\", the timer register is incremented in every falling or rising edge of T0CKI pin, depending on T0SE bit in OPTION register.
t0cki
Watchdog TimerThe watchdog timer is a free running timer. WDT has its own clock input, separate from system clock. It means, that the WDT will run, even if the system clock is stopped by execution of SLEEP instruction. During normal operation, a WDT timeout generates a Watchdog reset. If the device is in SLEEP mode, the WDT timeout causes the device to wake-up and continue with normal operation.
clkwdt
clk
por
Data bus The core internal data bus

Units

Hardware stack
The DFPIC165X configurable hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is pushed onto the stack when CALL instruction is executed or an interrupt causes a branch. The stack is popped while RETLW instruction is executed. The stack operates as a circular buffer - after the stack has been pushed two times, the third push overwrites the value, which was stored from the first push.
Control Unit
It performs the core synchronization and data flow control. This module manages execution of all instructions. Performs decode and control functions for all other blocks. It contains program counter (PC) and hardware stack.
ALU
Arithmetic Logic Unit - performs arithmetic and logic operations during execution of an instruction. This module contains work register (W) and Status register.

I/O Ports
I/O ports block contains DFPIC165X's general purpose I/O ports and data direction registers (TRIS). The DRPIC165X has three 8-bit full bi-directional ports PORT A, PORT B and PORT C. Read and write accesses to the I/O port are performed via their corresponding SFR's PORTA, PORTB, PORTC. The reading instruction always reads the status of Port pins. Writing instructions always write into the Port latches. Each port's pin has an corresponding bit in TRISA, TRISB and TRISC registers. When the bit of TRIS register is set, it means, that the corresponding bit of port is configured as an input (output drivers are set into the High Impedance).
RAM Controller
It performs interface functions between Data memory and DFPIC165X internal logic. It assures correct Data memory addressing and data transfers. The DFPIC165X supports two addressing modes: direct or indirect. In Direct Addressing, the 8-bit direct address is computed from FSR(7:5) bits and from 5 least significant bits of instruction word. Indirect addressing is possible, by using the INDF register. Any instruction using INDF register, actually accesses data pointed to by FSR (file select register). Reading INDF register indirectly, will produce 00h. Writing to the INDF register indirectly, results in a no-operation. An effective 8-bit address is obtained from an 8-bit FSR register.
Timer 0
Main system's timer and prescaler. It operates in two modes: 8-bit timer or 8-bit counter. In the \"timer mode\", timer/prescaler registers are incremented in every instruction cycle (1 or 2 CLK periods). When the prescaler is assigned into the TIMER, prescaler ratio can be divided by 2, 4, ..., 256. In the \"counter mode\", the timer register is incremented in every falling or rising edge of T0CKI pin, depending on T0SE bit in OPTION register.

Watchdog Timer
The watchdog timer is a free running timer. WDT has its own clock input, separate from system clock. It means, that the WDT will run, even if the system clock is stopped by execution of SLEEP instruction. During normal operation, a WDT timeout generates a Watchdog reset. If the device is in SLEEP mode, the WDT timeout causes the device to wake-up and continue with normal operation.