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D2692

Dual UART

    Dual UART IP Core

    The D26C92 is a Dual UART Core software compatible with the SC26C92, SCC2692 and SCN2681 with added features and deeper FIFOs.
    It contains: 8 character receiver, 8 character transmit FIFOs, watch dog timer for each receiver, mode register 0, extended baud rate, programmable receiver and transmitter interrupts.
    The D26C92 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a communication device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. It interfaces directly with microprocessors and may be used in a polled or interrupt driven system, furthermore provides modem and DMA interface. The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of 27 fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the  UART particularly attractive for dual-speed channel applications such as clustered terminal systems.

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    Family summary

    UART Feature DμART D2692 D16450 D16550 D16750 D16552 D16752 D16950 D85C30
    FIFO Size - 2*8 - 2*16 2*64 4*16 x*2*64 2*128 4
    Multichannel option - - - - - + + - -
    Separate BAUD Clock line + - + + + + + + +
    Modem Control - - + + + + + + +
    False Start Bit detection + + + + + + + + +
    Status report + + + + + + + + +
    Internal diagnostic capabilities + + + + + + + + +
    Prioritized interrupt system - + + + + + + + +
    Break generation and detection - + + + + + + + +
    Fast mode CLK/4 - - - - o - o + -
    Half-Duplex RS485 - + - - o - o + +
    RS485 buffer enable - - - + + - + + +
    IRDA support - - - - o + - + -
    Additional CLK prescaler - - - - - - + - -
    1284 Parallel Port - - - - - + - - -
    Hardware flow control RTS/CTS - + - - + - + + +
    Software flow control Xon/Xoff - - - - - - + + -
    Isochronous mode - - - - - - - + +
    Detector of bad data in receiver FIFO - + - + + + + + +
    Special character detection - - - - - - + + -
    Software channel reset - - - - - - - + -
    4 byte device ID - - - - - - - + -
    Trigger levels for receiver and transmitter - - - - - - - + -
    Hardware flow control DTS/DTR - - - - - - - + -
    Optional FIFO size extension to 512 bytes - - - - + - + - -

    The main features of each UART family member have been summarized in table above. It gives a briefly member characterization helping you to select the most suitable IP Core for your application.

    Performance

    D2692 has been tested in variety of FPGA and ASIC technologies.

    Implementation Speed grade Logic Cells MEMORY
    Bits
    Frequency [MHz]
    ARIA GX -6 1063/465 304 150
    ARIA V -6 1022/473 304 174
    CYCLONE -6 1434 304 125
    CYCLONE II -6 1474 304 148
    CYCLONE III -6 1493 304 180
    CYCLONE IV -6 1492 304 166
    CYCLONE V -6 1022/465 304 170
    STRATIX -5 1434 304 138
    STRATIX II -3 1057/465 304 212
    STRATIX III -2 1031/494 304 331
    STRATIX IV -2 1026/527 304 337
    STRATIX V -2 1056/490 304 339
    STRATIX GX -5 1434 304 135
    STRATIX2 GX -3 1057/465 304 218

    D2692 implementation results for ALTERA devices.
    All features have been included.

    Implementation Speed grade LUTs/Slices MEMORY
    Blocks
    Frequency [MHz]
    Artix 7 -3 857/382 4 216
    Kintex 7 -3 849/304 4 357
    Zynq -3 859/435 4 214
    Virtex 7 -2 854/428 4 320
    Virtex 6 -2 800/383 4 176
    Virtex 5 -2 860/296 4 226
    Virtex 4 -12 1383/837 4 155
    Spartan 6 -3 875/281 4 139
    Spartan 3E -5 1335/816 4 104
    Spartan 3 -5 1335/813 4 88

    D2692 implementation results for XILINX devices.
    All features have been included.

    Implementation Speed grade Logic Cells MEMORY
    Blocks
    Frequency [MHz]
    Fusion -2 3129 4 62
    ProASIC3 -2 3179 4 65
    ProASIC3E -2 3179 4 65
    SmartFusion -1 3129 4 62
    Igloo   3824 0 32
    Axcelerator -2 2181 4 95

    D2692 implementation results for ACTEL devices.
    All features have been included.


    Key Features

    • Software compatible with SC26C92, SCC2692 and SCN2681 UARTs
    • Configuration capability
    • Dual full-duplex independent asynchronous receiver/transmitters
    • 8 character FIFOs for each receiver and transmitter
    • Programmable data format:
      • 5 to 8 data bits plus parity
      • Odd, even, no parity or force parity
      • 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
    • 16-bit programmable Counter/Timer
    • Programmable baud rate for each receiver and transmitter selectable from:
      • 27 fixed rates: 50 to 230.4k baud
      • Other baud rates to 230.4k baud at 16X
      • Programmable user-defined rates derived from a programmable counter/timer
      • External 1X or 16X clock
    • Parity, framing, and overrun error detection
    • False start bit detection
    • Line break detection and generation
    • Programmable channel mode:
      • Normal (full-duplex)
      • Automatic echo
      • Local loopback
      • Remote loopback
      • Multidrop mode (also called
        ‘wake-up’ or ‘9-bit’)
    • Multi-function 7-bit input port:
      • Can serve as clock, modem, or control inputs
      • Change of state detection on four inputs
    • Multi-function 8-bit output port:
      • Individual bit set/reset capability
      • Outputs can be programmed to be status/interrupt signals
      • FIFO states for DMA and modem interface
    • Versatile interrupt system:
      • Single interrupt output with eight maskable interrupting conditions
      • Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs
      •  Each FIFO can be programmed for four different interrupt levels
      • Watch dog timer for each receiver
    • Maximum data transfer rates: 1X – 1Mb/sec, 16X – 1Mb/sec
    • Automatic wake-up mode for multidrop applications
    • Start-end break interrupt/status
    • Detects break which originates in the middle of a character
    • Power down mode
    • Receiver timeout mode

    Applications

    • Serial Data communications applications
    • Modem interface
    • Embedded microprocessor boards

    Symbol

     clk
     rst
     datai (7:0)
     rd
     wr
     cs
     addr (2:0)
    datao (7:0) 
    ddis 
    txrdy 
    rxrdy 
     int
     mclr
     prgdata (13:0)
    sleep 
    prgaddr (15:0) 
     baudclken
     baudclk
    baudout 
     t0cki

    Pins description

    PinTypeDescription
    clkinputGlobal clock
    rstinputGlobal reset
    datai (7:0)inputParallel data input
    rdinputRead input
    wrinputWrite input
    csinputChip select
    addr (2:0)inputAddress bus
    intinputExternal interrupt
    mclrinputUser reset
    prgdata (13:0)inputData bus from program memory
    baudclkeninputBaud generator clock enable
    baudclkinputBaud generator clock
    t0ckiinputTimer 0 input
    datao (7:0)outputParallel data output
    ddisoutputDriver disable output
    txrdyoutputTransmitter ready output
    rxrdyoutputReceiver ready output
    sleepoutputSleep signal
    prgaddr (15:0)outputProgram memory address bus
    baudoutoutputBaud generator output

    Block Diagram

    Data Bus BufferData Bus Buffer accepts inputs from the system bus and generates control signals for the other UART functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WR signals are active low and qualified by CS; RD and WR are ignored unless the UART has been selected by holding CS low.
    datai (7:0)
    datao (7:0)
    rd
    wr
    cs
    ddis
    txrdy
    rxrdy
    addr (2:0)
    Interrupt ControllerInterrupt Controller module is responsible for interrupt manage system for the external and internal interrupt sources. It contains interrupt related register, called INTCON. There are three interrupt sources:
    • External interrupt INT
    • TMR0 overflow interrupt
    • PORTB change interrupt (pins B[7:4])
    INTCON records individual interrupt requests in flag bits. A global interrupt enable (GIE) bit enables all unmasked interrupts. Each interrupt source, has an individual enable bit, which can enable or disable corresponding interrupt. When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. The interrupt flag bits must be cleared in software before re-enabling interrupts.
    int
    Control UnitIt performs the core synchronization and data flow control. This module manages execution of all instructions. It carries out the decode and control functions for all other blocks. It contains program counter (PC) and hardware stack.
    mclr
    sleep
    prgdata (13:0)
    prgaddr (15:0)
    Baud GeneratorThe UART contains a programmable 16 bit baud generator, that divides clock input by a divisor, in the range between 1 and (216-1). The output frequency of the baud generator is 16× the baud rate. The formula for the divisor is:

    divisor=frequency/(16*baudrate)

    Two 8-bit registers, called divisor latches DLL and DLM, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded on the CLK rising edge following the write to DLL or DLM, to prevent long counts on initial load.
    baudout
    baudclken
    baudclk
    Timer 0Main system's timer and prescaler. It operates in two modes: 8-bit timer or 8-bit counter. In the \"timer mode\", timer/prescaler registers are incremented in every instruction cycle (1 or 2 CLK periods). When the prescaler is assigned into the TIMER, prescaler ratio can be divided by 2, 4, ..., 256. In the \"counter mode\", the timer register is incremented in every falling or rising edge of T0CKI pin, depending on T0SE bit in OPTION register.
    t0cki
    clk
    rst
    D16550 D16XXX UART internal data bus
    Data bus The core internal data bus

    Units

    Data Bus Buffer
    Data Bus Buffer accepts inputs from the system bus and generates control signals for the other UART functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WR signals are active low and qualified by CS; RD and WR are ignored unless the UART has been selected by holding CS low.
    Interrupt Controller
    Interrupt Controller module is responsible for interrupt manage system for the external and internal interrupt sources. It contains interrupt related register, called INTCON. There are three interrupt sources:
    • External interrupt INT
    • TMR0 overflow interrupt
    • PORTB change interrupt (pins B[7:4])
    INTCON records individual interrupt requests in flag bits. A global interrupt enable (GIE) bit enables all unmasked interrupts. Each interrupt source, has an individual enable bit, which can enable or disable corresponding interrupt. When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. The interrupt flag bits must be cleared in software before re-enabling interrupts.
    Control Unit
    It performs the core synchronization and data flow control. This module manages execution of all instructions. It carries out the decode and control functions for all other blocks. It contains program counter (PC) and hardware stack.

    Baud Generator
    The UART contains a programmable 16 bit baud generator, that divides clock input by a divisor, in the range between 1 and (216-1). The output frequency of the baud generator is 16× the baud rate. The formula for the divisor is:

    divisor=frequency/(16*baudrate)

    Two 8-bit registers, called divisor latches DLL and DLM, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded on the CLK rising edge following the write to DLL or DLM, to prevent long counts on initial load.
    Timer 0
    Main system's timer and prescaler. It operates in two modes: 8-bit timer or 8-bit counter. In the \"timer mode\", timer/prescaler registers are incremented in every instruction cycle (1 or 2 CLK periods). When the prescaler is assigned into the TIMER, prescaler ratio can be divided by 2, 4, ..., 256. In the \"counter mode\", the timer register is incremented in every falling or rising edge of T0CKI pin, depending on T0SE bit in OPTION register.