Digital Core Design

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DUART

Tiny UART

    Small is beautiful...
    The DμART is one of the tiniest UART IP Cores available on the market.

    The DμART is a soft core of a Universal Asynchronous Receiver/Transmitter (UART). It performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (overrun, framing). The DμART includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. The DμART has processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link.

    The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices.

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    Family summary

    UART Feature DμART D2692 D16450 D16550 D16750 D16552 D16752 D16950 D85C30
    FIFO Size - 2*8 - 2*16 2*64 4*16 x*2*64 2*128 4
    Multichannel option - - - - - + + - -
    Separate BAUD Clock line + - + + + + + + +
    Modem Control - - + + + + + + +
    False Start Bit detection + + + + + + + + +
    Status report + + + + + + + + +
    Internal diagnostic capabilities + + + + + + + + +
    Prioritized interrupt system - + + + + + + + +
    Break generation and detection - + + + + + + + +
    Fast mode CLK/4 - - - - o - o + -
    Half-Duplex RS485 - + - - o - o + +
    RS485 buffer enable - - - + + - + + +
    IRDA support - - - - o + - + -
    Additional CLK prescaler - - - - - - + - -
    1284 Parallel Port - - - - - + - - -
    Hardware flow control RTS/CTS - + - - + - + + +
    Software flow control Xon/Xoff - - - - - - + + -
    Isochronous mode - - - - - - - + +
    Detector of bad data in receiver FIFO - + - + + + + + +
    Special character detection - - - - - - + + -
    Software channel reset - - - - - - - + -
    4 byte device ID - - - - - - - + -
    Trigger levels for receiver and transmitter - - - - - - - + -
    Hardware flow control DTS/DTR - - - - - - - + -
    Optional FIFO size extension to 512 bytes - - - - + - + - -

    The main features of each UART family member have been summarized in table above. It gives a briefly member characterization helping you to select the most suitable IP Core for your application.

    Performance

    DμART has been tested in variety of FPGA and ASIC technologies. Example Altera implementation results are summarized below.

    Implementation Speed grade Area [LC] MEMORY
    Bits
    Frequency [MHz]
    ARIA GX -6 143/130 - 267
    ARIA V -6 100/141 - 315
    CYCLONE -6 218 - 226
    CYCLONE II -6 218 - 297
    CYCLONE III -6 227 - 335
    CYCLONE IV -6 223 - 317
    CYCLONE V -6 102/141 - 265
    STRATIX -5 218 - 244
    STRATIX II -3 144/131 - 404
    STRATIX III -2 146/130 - 542
    STRATIX IV -2 146/130 - 605
    STRATIX V -2 95/148 - 637
    STRATIX GX -5 218 - 242
    STRATIX2 GX -3 218 - 176
    MAX II -4 218   91

    DμART implementation results for ALTERA devices.
    All features have been included.

    Device Speed grade LUTs/Slices Frequency [MHz]
    Zynq -3 153/83 331
    Kintex 7 -3 153/83 517
    Artix 7 -3 114/77 394
    Virtex 7 -2 153/85 588
    Virtex 6 -2 126/70 341
    Virtex 5 -2 144/70 400
    Virtex 4 -12 183/141 388
    Spartan 6 -3 132/52 287
    Spartan 3E -5 173/143 186
    Spartan 3 -5 173/144 171
    XC9500 -7 135 76

    DμART implementation results for XILINX devices.
    All features have been included.


    Key Features

    • Majority Voting Logic
    • Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
    • In UART mode receiver and transmitter are double buffered to eliminate the need for precise synchronization between the CPU and serial data
    • Independently controlled transmit, receive, line status, and data set interrupts
    • 16 bit programmable baud generator
    • False start bit detection
    • Line break generation and detection. Internal diagnostic capabilities:
      • Loop-back controls for communications link fault isolation
      • Overrun, framing error detection
    • Full prioritized interrupt system controls
    • Technology independent HDL Source Code
    • Fully synthesizable static design with no internal tri-state buffers

    Applications

    • Serial Data communications applications
    • Modem interface
    • Embedded microprocessor boards

    Symbol

     clk
     rst
     datai (7:0)
     rd
     wr
     cs
     addr (2:0)
    datao (7:0) 
     rclk
     si
    so 
    temt 
    intr 

    Pins description

    PinTypeDescription
    clkinputGlobal clock
    rstinputGlobal reset
    datai (7:0)inputParallel data input
    rdinputRead input
    wrinputWrite signal input
    csinputChip select input
    addr (2:0)inputAddress bus input
    rclkinputReceiver clock
    siinputSerial data input
    datao (7:0)outputParallel data bus output
    sooutputSerial data output
    temtoutputTransmitter Empty - used to control RS485 buffer
    introutputInterrupt request output

    Block Diagram

    Data Bus BufferData Bus Buffer accepts inputs from the system bus and generates control signals for the other UART functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WR signals are active low. Both RD and WR are qualified by CS; RD and WR are ignored unless the UART has been selected by holding CS low.
    datai (7:0)
    rd
    wr
    cs
    addr (2:0)
    datao (7:0)
    Receiver ControlThe D16X50 receiver has its own independent clock input RCLK. Receiving starts when the falling edge on Serial Input (SI) during IDLE State is being detected. After starting, the SI input is sampled every 16 RCLK cycles, as it is shown in figure below. When the logic 1 state is detected during START bit, it means that the False Start bit was detected and receiver back to the IDLE state.
    rclk
    si
    Transmitter ControlTransmitter Control module controls transmission of written to THR (Transmitter Holding Register) character via serial output SO. New transmission starts on the next overflow signal of internal baud generator (the worst case delay: 1 baudout cycle), after writing to THR register or Transmitter FIFO. Transmission control contains THR register and transmitter shift register.
    so
    temt
    Interrupt ControllerD16X50 UARTs got fully prioritized interrupt system controller. It controls interrupt requests to the CPU and interrupt priority. Interrupt controller contains Interrupt Enable (IER) and Interrupt Identification (IIR) registers.
    intr
    clk
    rst
    D16550 D16XXX UART internal data bus

    Units

    Data Bus Buffer
    Data Bus Buffer accepts inputs from the system bus and generates control signals for the other UART functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WR signals are active low. Both RD and WR are qualified by CS; RD and WR are ignored unless the UART has been selected by holding CS low.
    Receiver Control
    The D16X50 receiver has its own independent clock input RCLK. Receiving starts when the falling edge on Serial Input (SI) during IDLE State is being detected. After starting, the SI input is sampled every 16 RCLK cycles, as it is shown in figure below. When the logic 1 state is detected during START bit, it means that the False Start bit was detected and receiver back to the IDLE state.
    Transmitter Control
    Transmitter Control module controls transmission of written to THR (Transmitter Holding Register) character via serial output SO. New transmission starts on the next overflow signal of internal baud generator (the worst case delay: 1 baudout cycle), after writing to THR register or Transmitter FIFO. Transmission control contains THR register and transmitter shift register.

    Interrupt Controller
    D16X50 UARTs got fully prioritized interrupt system controller. It controls interrupt requests to the CPU and interrupt priority. Interrupt controller contains Interrupt Enable (IER) and Interrupt Identification (IIR) registers.