Digital Core Design

The Power of Intellectual Property

The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, no matter if it’s 8-, 16- or 32-bit microcontroller. It allows to save MCU time wasted for handling HDLC/SDLC features like bit stuffing, address recognition or CRC computation. The DHDLC has implemented FIFO buffer, for both, receiver and transmitter.


Performance

Implementation Logic Cells Memory Bits Frequency [MHz]
Aria 517/363 256 179
Aria 2 510/360 256 260
Aria 5 507/443 256 204
Cyclone 767 256 140
Cyclone 2 787 256 160
Cyclone 3 785/359 256 188
Cyclone 4 789/359 256 199
Cyclone 5 507/359 256 183
Stratix 767/336 256 169
Stratix 2 511/359 256 260
Stratix 3 507/391 256 383
Stratix 4 510/392 256 384
Stratix 5 511/440 256 385

DHDLC implementation results for ALTERA devices.

Implementation LUTs/Slices Memory Blocks Frequency [MHz]
Kintex 7 526/225 2 410
Zynq 509/255 2 270
Artix 7 480/212 2 289
Virtex 7 523/242 2 417
Virtex 6 475/201 2 281
Virtex 5 487/215 2 271
Virtex 4 623/469 2 221
Spartan 6 525/193 2 178
Spartan 3E 620/472 2 129
Spartan 3 607/462 2 123

DHDLC implementation results for XILINX devices.


Key Features

  • Two separate receiver and transmitter interfaces.
  • Two separate, configurable FIFO buffers for receiver and transmitter
  • Bit stuffing and unstuffing
  • Address recognition for receiver and address insertion for transmitter
  • Two or one byte address field
  • RC-16 and CRC-32 computation and checking
  • Collision detection
  • Byte alignment error detection
  • Programmable number of bits for idle detection
  • NRZI coding support
  • Shared flags, shared zeros support
  • Pad fill with flags option
  • Transmitter clock generation
  • 8-bit, 16-bit, 32-bit CPU interface
  • Interrupt output for handling control flags and FIFOs’ filling
  • Configurable core parameters
     

Applications

  • CPU based applications with serial interface based on HDLC/SDLC protocol
  • Telecommunication

Design Features

The DHDLC IP core is full synchronous with one clock domain design. All parameters are configurable by CPU. But there is also capability for setting parameters by modification constants in source file. There is no need to wasting silicon resources for unused features and constant settings.


Symbol

 rst
 clk
 addr (3:0)
 datai (7:0)
 wr
 rd
 cs
datao (7:0) 
irq 
 rxd
 rxclk
 txclk
txd 
txclko 
 cxd
txclken 
 rxdatai (7:0)
 txdatai (7:0)
rxdatao (7:0) 
rxwraddr (3:0) 
rxrdaddr (3:0) 
rxrd 
rxwr 
txdatao (7:0) 
txrdaddr (3:0) 
txwraddr (3:0) 
txrd 
txwr 

Pins description

PinTypeDescription
rstinputGlobal reset
clkinputGlobal clock
addr (3:0)inputCPU address bus input
datai (7:0)inputCPU Data bus input
wrinputCPU write
rdinputCPU read signal
csinputDHDLC Chip Select input
rxdinputReceiver serial data input
rxclkinputReceiver clock input
txclkinputTransmitter clock input
cxdinputCollision detect input
rxdatai (7:0)inputRX FIFO data input
txdatai (7:0)inputTX FIFO data input
datao (7:0)outputCPU Data bus output
irqoutputDHDLC Interrupt request to CPU
txdoutputTransmitter serial data output
txclkooutputTransmitter clock output
txclkenoutputTransmitter clock output enable
rxdatao (7:0)outputRX FIFO data output
rxwraddr (3:0)outputRX FIFO Write Address
rxrdaddr (3:0)outputRX FIFO read address
rxrdoutputRX FIFO read
rxwroutputRX FIFO write
txdatao (7:0)outputTX FIFO data output
txrdaddr (3:0)outputTX FIFO read address
txwraddr (3:0)outputTX FIFO write address
txrdoutputTX FIFO read
txwroutputTX FIFO write

Block Diagram

CPU InterfacePerforms operations of reading and writing internal registers of the IP core. It also manages interrupt activity, sets and clears flags.
addr (3:0)
datai (7:0)
datao (7:0)
wr
rd
cs
irq
Serial InterfaceDirect HDLC/SDLC interface. Realizes tasks of bit stuffing and unstuffing, NRZI coding, collision detection, CRC calculation, flags and abort detection, idle detection and synchronizes serial inputs with main clock domain
rxd
rxclk
txd
txclk
txclko
Control UnitMain control unit. This module is responsible for managing other blocks. Mainly it controls and services requests from CPU interface module and forms data for HDLC frame. It also realizes some features of HDLC control like address recognition and insertion, padding, etc.
cxd
Clock DividerGenerates divided clock signal for TXCLKO output.
txclken
FIFO ControlManages access to FIFO buffers of receiver and transmitter. It also generates current state of FIFO flags. The flags indicates, among others, that FIFO are empty or full. It also indicates events of FIFO's under or overflowing.
rxdatai (7:0)
rxdatao (7:0)
rxwraddr (3:0)
rxrdaddr (3:0)
rxrd
rxwr
txdatai (7:0)
txdatao (7:0)
txrdaddr (3:0)
txwraddr (3:0)
txrd
txwr
rst
clk
Control Bus

Units

CPU Interface
Performs operations of reading and writing internal registers of the IP core. It also manages interrupt activity, sets and clears flags.
Serial Interface
Direct HDLC/SDLC interface. Realizes tasks of bit stuffing and unstuffing, NRZI coding, collision detection, CRC calculation, flags and abort detection, idle detection and synchronizes serial inputs with main clock domain
Control Unit
Main control unit. This module is responsible for managing other blocks. Mainly it controls and services requests from CPU interface module and forms data for HDLC frame. It also realizes some features of HDLC control like address recognition and insertion, padding, etc.

Clock Divider
Generates divided clock signal for TXCLKO output.
FIFO Control
Manages access to FIFO buffers of receiver and transmitter. It also generates current state of FIFO flags. The flags indicates, among others, that FIFO are empty or full. It also indicates events of FIFO's under or overflowing.