Digital Core Design

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DMAC-RMII

10/100 Mb Media Access Controller with RMII

    Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. The DMAC-RMII in cooperation with external PHY device enables network functionality in design. It is capable to transmit and receive Ethernet frames to and from the network. Half and full duplex modes are supported, as well 10 and 100 Mbit/s speed. The Core is able to work with wide range of processors: 8, 16 and 32 bit data bus, either little or big endian byte order format. The DMAC-RMII provides static configuration of PHY IC. Please remember that our design is technology independent and thus can be implemented in variety of process technologies. This Core strictly conforms to the IEEE 802.3 standard.

    Watch the DMAC-RMII presentation on DCD's You Tube:

    Subskrybuj mój kanał w YouTube


    Performance

    Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.

    Implementation Speed
    grade
    Utilized Area
    [Slices/LUTs]
    Frequency
    [MHz]
    clk / rmiiclk
    VIRTEX-6 -2 352/911+4kB RAM 275 / 240
    VIRTEX-5 -2 475/985+4kB RAM 250 / 200
    VIRTEX-4 -12 898/1347+4kB RAM 165 / 165
    VIRTEX-II -6 890/1335+4kB RAM 150 / 120
    SPARTAN-6 -3 353/890+4kB RAM 115 / 140
    SPARTAN-3E -5 895/1333+4kB RAM 110 / 90
    SPARTAN-3 -5 898/1341+4kB RAM 100 / 85

    DMAC-RMII implementation results for XILINX devices.
    All features have been included. 

    Implementation Speed
    grade
    Utilized Area
    [LC]
    Frequency
    [MHz]
     clk / rmiiclk
    STRATIX IV -1 896+4kB RAM 420 / 350
    STRATIX III -2 898+4kB RAM 400 / 350
    STRATIX II -3 892+4kB RAM 300 / 260
    CYCLONE IV -6 1341+4kB RAM 200 / 200
    CYCLONE III -6 1342+4kB RAM 190 / 190
    CYCLONE II -6 1340+4kB RAM 158 / 170
    STRATIX GX -5 1255+4kB RAM 152 / 138
    STRATIX  -5 1255+4kB RAM 162 / 137
    CYCLONE -6 1254+4kB RAM 148 / 133

    DMAC-RMII implementation results for ALTERA devices.
    All features have been included. 

    Implementation

    Speed
    grade
    Minimum Area
    [gates]
    Top Frequency
    Fmax [MHz]
    clk / rmiiclk
    0.25 um typical 7900 gates 250 / >50
    0.18 um typical 7900 gates 360 / >50
    0.09 um typical 6500 gates 800 / >50
    0.06 um typical 6400 gates 900 / >50
    0.04 um typical 6400 gates 1000 / >50

    DMAC-RMII implementation results for ASIC devices.
    All features have been included. 


    Key Features

    • Conforms to IEEE 802.3-2002 specification
    • Configurable width CPU interface with little or big endianess:
      • 8-bit
      • 16-bit
      • 32-bit
    • Simple interface allows easy connection to CPU
    • Narrow address bus (4 bits) with indirect I/O interface for transmitted and received data dual port memories
    • Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs
    • Reduced Media Independent Interface (RMII) for connection to external 10/100 Mbps PHY transceivers
    • Supports full and half duplex operation at 10 Mbps or 100 Mbps
    • CRC-32 algorithm:
      • calculates the FCS nibble at a time
      • automatic FCS generation and checking
      • able to capture frames with CRC errors if required
    • Dynamic PHY configuration by STA management interface
    • Early receive and transmit interrupts to increase data throughput
    • Programmable MAC address
    • Promiscuous mode support
    • Allows operation from a wide range of input bus clock frequencies
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking
    • No internal tri-states
    • Lite design, small gate count and fast operation
    • Scan test ready

    Applications

    • Embedded microprocessor boards
    • Networking devices (Network Interface Cards, routers, switches)
    • Communication systems

    Symbol

     qmt (31:0)
    dmt (31:0) 
    waddrmrt (8:0) 
    raddrmt (8:0) 
    enrmt 
    enwmt 
     rmiiclk
     mb100
    rmiitxen 
    rmiitxd (1:0) 
     mdi
    mdoe 
    mdo 
    mdc 
     qmr (31:0)
    waddrmr (8:0) 
    raddrmr (8:0) 
    enwmr 
    enrmr 
    dmr (31:0) 
     rmiirxer
     rmiicrsdv
     rmiirxd (1:0)
     wr
     rd
     datai1 (31:0)
     clk
     be1 (3:0)
     addr (3:0)
     rst
    irq 
    datao1 (31:0) 

    Pins description

    PinTypeDescription
    qmt (31:0)inputTX DPRAM data output
    rmiiclkinputRMII 50 MHz reference clock
    mb100inputSelect 100 Mb speed
    mdiinputManagement data input
    qmr (31:0)inputRX DPRAM data output
    rmiirxerinputRMII receive error
    rmiicrsdvinputRMII carier sense/receive valid
    rmiirxd (1:0)inputRMII receive data
    wrinputWrite data strobe
    rdinputRead data strobe
    datai1 (31:0)inputHost output data bus
    clkinputGlobal clock
    be1 (3:0)inputHost byte enable
    addr (3:0)inputHost address bus
    rstinputGlobal reset
    dmt (31:0)outputTX DPRAM data input
    waddrmrt (8:0)outputTX DPRAM write address
    raddrmt (8:0)outputTX DPRAM read address
    enrmtoutputTX DPRAM read enable
    enwmtoutputTX DPRAM write enable
    rmiitxenoutputRMII transmit enable
    rmiitxd (1:0)outputRMII transmit data
    mdoeoutputManagement data output enable
    mdooutputManagement data output
    mdcoutputManagement clock
    waddrmr (8:0)outputRX DPRAM write address
    raddrmr (8:0)outputRX DPRAM read address
    enwmroutputRX DPRAM write enable
    enrmroutputRX DPRAM read enable
    dmr (31:0)outputRX DPRAM data input
    irqoutputInterrupt signal
    datao1 (31:0)outputHost input data bus

    Block Diagram

    TX RAM InterfaceInterfaces to external dual port memories, used by the DMAC-RMII core to store transmitted frames.
    qmt (31:0)
    dmt (31:0)
    waddrmrt (8:0)
    raddrmt (8:0)
    enrmt
    enwmt
    Transmit modulePerforms transmit management functions, sends frames to Ethernet medium. It is responsible for proper frame creation and response to PHY signals.
    rmiitxen
    rmiitxd (1:0)
    rmiiclk
    mb100
    Synchronization logicThere are 3 clock domains in the DMAC-RMII core. This module performs synchronization between these domains and assures correct data exchange between these domains.
    STA interfaceStation Management entity provides capability to communicate with PHY by simple serial management interface and dynamically setup transmission parameters. PHY can be configured by DMAC-RMII at any time, allowing easy management of PHY behavior.
    mdoe
    mdo
    mdi
    mdc
    RX RAM InterfaceInterfaces to external dual port memories, used by the DMAC-RMII core to store received frames.
    waddrmr (8:0)
    raddrmr (8:0)
    qmr (31:0)
    enwmr
    enrmr
    dmr (31:0)
    Receive moduleThis module is responsible for receiving frames from the Ethernet. Provides necessary functions for frame decapsulation, CRC checking, address recognizing and error detection.
    rmiirxer
    rmiicrsdv
    rmiirxd (1:0)
    Control and I/O logicThis module provides interface to CPU/BUS. It exchanges data and control logic with transmit and receive modules, thus controls these to perform transmit and receive operations. Proper data alignment and bytes order is performed inside this unit.
    1 - data bus can be configured as 8-, 16- or 32- bit depends on processor's bus size
    wr
    rd
    irq
    datao1 (31:0)
    datai1 (31:0)
    clk
    be1 (3:0)
    addr (3:0)
    rst

    Units

    TX RAM Interface
    Interfaces to external dual port memories, used by the DMAC-RMII core to store transmitted frames.
    Transmit module
    Performs transmit management functions, sends frames to Ethernet medium. It is responsible for proper frame creation and response to PHY signals.
    Synchronization logic
    There are 3 clock domains in the DMAC-RMII core. This module performs synchronization between these domains and assures correct data exchange between these domains.

    STA interface
    Station Management entity provides capability to communicate with PHY by simple serial management interface and dynamically setup transmission parameters. PHY can be configured by DMAC-RMII at any time, allowing easy management of PHY behavior.
    RX RAM Interface
    Interfaces to external dual port memories, used by the DMAC-RMII core to store received frames.
    Receive module
    This module is responsible for receiving frames from the Ethernet. Provides necessary functions for frame decapsulation, CRC checking, address recognizing and error detection.

    Control and I/O logic
    This module provides interface to CPU/BUS. It exchanges data and control logic with transmit and receive modules, thus controls these to perform transmit and receive operations. Proper data alignment and bytes order is performed inside this unit.
    1 - data bus can be configured as 8-, 16- or 32- bit depends on processor's bus size