- USB [IP Core] combo pack from DCD
- Success Story: Myson Century: “Outstanding performance” - the core advantage of DCD’s 8051 family
- Success Story: ASIX: The key to new network solutions.
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- Success Story: Avisonic Chooses DCD’s DP8051 for Image Processors
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The DP8051CPU is an ultra high performance, speed optimized soft core, of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management PMU unit.
The DP8051CPU soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of DP8051CPU: Harvard, where internal data and program buses are separated and von Neumann, with common program and external data bus. The DP8051CPU has a Pipelined RISC architecture and executes 120-300 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster, than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51 with the same settings. This performance can also be exploited to great advantage in low power applications, where the core can be clocked over ten times more slower than the original implementation, without performance depletion.
The DP8051CPU is delivered with fully automated testbench and complete set of tests, allowing easy package validation, at each stage of SoC design flow.
Each of the DCD's 8051 Core has built-in support for DCD Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. More details about DCD on Chip Debugger
The main features of each DCD's DQ8051, DQ80251, DP8051, DP80C51, DT8051 family member have been summarized in the table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and request the core modifications.
Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.
|0.25u area||typical||6 050||100|
|0.25u speed||typical||7 600||250|
|0.18u area||typical||5 730||100|
|0.18u speed||typical||6 900||300|
DP8051CPU implementation results for ASIC devices - results given for working system, with connected IDATA, CODE and XDATA memories. The CPU features and Peripherals have been included. DoCD TTAG debugger increases core size by approximately 1 800 gates.
|VIRTEX-II pro||-7||860 Slices||129|
DP8051CPU implementation results for XILINX devices - results given for working system, with connected IDATA, CODE and XDATA memories.
|ARRIA GX||-6||1230 ALUT||112|
DP8051CPU implementation results for ALTERA devices - results given for working system, with connected IDATA, CODE and XDATA memories. The CPU features and Peripherals have been included.
DP8051CPU implementation results for LATTICE devices - results given for working system with connected IDATA, CODE and XDATA memories.
- software is 100% compatible with 8051 industry standard
- Pipelined RISC architecture enables to run 15.55 times faster, than the original 80C51 at the same frequency
- Up to 16,632 VAX MIPS at 100 MHz
- 24 times faster multiplication
- 12 times faster division
- Up to 256 bytes of internal (on-chip) Data Memory
- Up to 64 kB of internal (on-chip) or external (off-chip) Program Memory
- Up to 8MB linear code space (in 80390 mode)
- Up to 16 MB of external (off-chip) Data Memory
- User programmable Program Memory Wait States
- User programmable External Data Memory Wait States
- De-multiplexed Address/Data bus to allow easy memory connection
- Interface for additional Special Function Registers
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available
|iprgramsize (2:0)||input||Size of on-chip RAM CODE|
|iprgromsize (2:0)||input||Size of on-chip ROM CODE|
|int0||input||External interrupt 0|
|int1||input||External interrupt 1|
|sfrdatai (7:0)||input||Data bus from user SFRs|
|prgramdata (7:0)||input||Data bus from internal RAM program memory|
|prgromdata (7:0)||input||Data bus from internal ROM program memory|
|xdatai (7:0)||input||Data bus from external memories|
|ready||input||External memory data ready|
|ramdatai (7:0)||input||Data bus from internal data memory|
|tdi||input||DoCDTM TAP data input|
|tck||input||DoCDTM TAP clock line|
|tms||input||DoCDTM TAP mode select|
|sxdmdatai (7:0)||input||Data bus from sync external data memory (SXDM)|
|sfrdatao (7:0)||output||Data bus for user SFRs|
|sfrwe||output||User SFRs write enable|
|sfroe||output||User SFRs read|
|sfraddr (6:0)||output||User SFRs address bus|
|prgaddr (15:0)||output||Internal program memory address bus|
|prgdatao (7:0)||output||Data bus for internal program memory|
|prgramwr||output||Internal program memory write|
|xdatao (7:0)||output||Data bus for external memories|
|xdataz||output||Turn xdata bus into "Z" state|
|xaddr (23:0)||output||Address bus for external memories|
|xprgrd||output||External program memory read|
|xprgwr||output||External program memory write|
|xdatard||output||External data memory read|
|xdatawr||output||External data memory write|
|stop||output||Stop mode indicator|
|pmm||output||Power management mode indicator|
|ramdatao (7:0)||output||Data bus for internal data memory|
|ramaddr (7:0)||output||RAM address bus|
|ramoe||output||Internal data memory read|
|ramwe||output||Internal data memory write enable|
|tdo||output||DoCDTM TAP data output|
|rtck||output||DoCDTM return clock|
|sxdmaddr (15:0)||output||Sync XDATA memory address bus (SXDM)|
|sxdmdatao (7:0)||output||Data bus for Sync XDATA memory (SXDM)|
|sxdmoe||output||Sync XDATA memory read (SXDM)|
|sxdmwe||output||Sync XDATA memory write (SXDM)|
|Opcode DecoderPerforms an opcode decoding instruction and control functions for all other blocks.|
|Control UnitIt performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and it manages execution of all microcontroller tasks.|
|ALUArithmetic Logic Unit - performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic, like arithmetic unit, logic unit, multiplier and divider.|
|Interrupt ControllerInterrupt Controller module is responsible for the interrupt manage system of the external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IP) and (TCON) registers.|
|SFRs InterfaceSpecial Function Registers interface - controls access to externally connected peripherals, through SFR bus.|
|Program Memory InterfaceProgram Memory Interface contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader, to load new program into ROM, RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCD module.|
|External Memory InterfaceContains memory access related registers, such as Data Page High (DPH), Data Page Low (DPL) and Data Page Pointer (DPP) registers. It performs the external Program and Data Memory addressing and data transfers. Program fetch cycle length can be programmed by the user. This feature is called Program Memory Wait States and it allows core, to work with different speed program memories.|
|Power Management UnitPower Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It is highly desirable, when microcontroller is planned to be used in portable and power critical applications.|
|Internal Data Memory InterfaceInterface controls access into the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.|
|DoCDTM TTAG DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware watchpoints can be set and controlled on internal and external data memories and also on SFRs. Hardware watchpoints are executed, if any write/read occurs at particular address, with certain data pattern or without pattern. Two additional pins: CODERUN and DEBUGACS, indicate the state of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCDTM debugger. The DoCDTM system includes TTAG interface and complete set of tools, to communicate and work with core in real time debugging. It is built, as a scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.|
|SXDM interfaceSynchronous eXternal Data Memory (SXDM) Interface contains XDATA memory access related logic, allowing fast access to synchronous memory devices. It performs the external Data Memory addressing and data transfers. This memory can be used to store large variables, frequently accessed by CPU, improving overall performance of application.|
|Internal data bus 8-bit internal data bus|
|SFR data bus 8-bit Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture.|