Digital Core Design

The Power of Intellectual Property

DQ80251

Revolutionary Quad-Pipelined Ultra High Performance Microcontroller

The DQ80251 is a revolutionary Quad-Pipelined ultra high performance, speed optimized soft core of a 16-bit/32-bit embedded microcontroller. The core is fully configurable and allows selection of its features and peripherals, to create a dedicated system. It has been designed with a special concern of performance to power consumption ratio. This ratio is extended by an advanced power management PMU unit. This product is built based on 15 years of DCD’s know-how, with triumphant 8051 architectures. The DQ80251 soft core is 100% binary-compatible with industry standard 16-bit 80C251 and 8-bit 80C51 microcontrollers. There are two working modes of the DQ80251: BINARY (where the original 80C51 compiled code is executed) and SOURCE (a native 80C251 mode, using all DQ80251 performance). The DQ80251 has a built-in, configurable DoCD-JTAG on chip debugger, supporting Keil DK251 and standalone DoCD debug software. Dhrystone 2.1 benchmark program runs more than 75 times faster than the original 80C51 and 6 times faster, than the original 80C251 at the same frequency. This performance can be also exploited to great advantage in low power applications, where the core can be clocked over fifty times slower than the original implementation, with no performance penalty. Additionally, the compiled code size for the SOURCE mode is about 2 times smaller comparing to the identical standard 8051 code, due to higher efficency of DQ80251 instructions.

The DQ80251 is delivered with fully automated testbench and complete set of tests, allowing easy package validation at each stage of SoC design flow.

Each of our 80251 cores has a built-in support for DCD's Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of the microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. More details about DCD's on-chip Debugger

Watch the DQ80251 presentation on DCD's You Tube:

Subskrybuj mój kanał w YouTube


Family summary

 

Design Dhry
speed
on-chip
CODE
RAM/ROM
off-chip
CODE
CODE
write
IDATA
space
XDATA
space
XDATA,
CODE
wait states
DoCDTM PMU Interrupt
sources
DPTR Timers UART IO Ports Compare/
Capture
Watchdog MDU
MDU32
DI2CM DI2CS DSPI DFPMU DMAC DCAN
DQ80251 75.08 8M 8M + 1k-32k 8M + + +  15 1 3 2 4 + + + + + + + + +
DQ8051CPU 28.40 64k/64k 64k/8M + 256 16M + + +  2 2 - - - - - - - - - - - -
DQ8051 29.01 64k/64k 64k/8M + 256 16M + + +  5 2 2 1 4 - - - - - - - - -
DQ8051XP 29.01 64k/64k 64k/8M + 256 16M + + + 15 2 3 2 4 + + + + + + + + +
DP8051CPU 15.36 64k/64k 64k/8M + 256 16M + + +  2 1 - - - - - - - - - - - -
DP8051 15.36 64k/64k 64k/8M + 256 16M + + +  5 1 2 1 4 - - - - - - - - -
DP8051XP 15.55 64k/64k 64k/8M + 256 16M + + + 15 2 3 2 4 + + + + + + + + +
DP80C51 11.46 64k/64k 64k + 256 64k + + +  5 1 2 1 4 - - - - - - - - -
DT8051 8.11 64k/64k 64k + 256 64k - + + 11 1 2 1 1 - - - - - - - - -

The main features of each DCD's DQ8051, DQ80251, DP8051, DP80C51, DT8051 family member have been summarized in the table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and request the core modifications.

Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

Implementation
device
Speed
grade
Area Min
[gates]
Area Full
[gates]
Top frequency
[MHz]
0.18 um  typical   14 500 23 600 150
0.13 um typical 14 200 23 000 200
0.09 um typical 13 500 21 700 300

DQ80251 core area and performance in ASIC devices - results given for working system  with connected CODE and DATA memories. All CPU features and Peripherals have been included.  DoCD JTAG debugger increases core size by approximately 2 900 gates.  


 


CPU Features


Symbol

 reset
 clk
 idmdatai
idmdatao 
idmaddr 
idmoe 
idmwe 
 t0
 t1
 gate0
 gate1
 rxd0i
rxd0o 
txd0 
 capture0
 capture1
 capture2
 capture3
 t2
 t2ex
 scli
 sdai
sclo 
sclhs 
sdao 
 xdmdatai
 xdmready
xdmdatao 
xdmdataz 
xdmaddr 
xdmbe 
xdmrd 
xdmwr 
xdmce 
 int0
 int1
 prgdatai
 prgready
prgdatao 
prgdataz 
prgaddr 
prgbe 
prgrd 
prgwr 
 sfrdatai
sfrdatao 
sfrraddr 
sfrwaddr 
sfroe 
sfrwe 
 tdi
 tck
 tms
tdo 
rtck 
debugacs 
coderun 
 port0i
 port1i
 port2i
 port3i
port0o 
port1o 
port2o 
port3o 
stop 
pmm 
 rtcclk
 rtcrst
 rxd1i
rxd1o 
txd1 
 mosi
 miso
 ss
 sck
sso (7:0) 

Pins description

PinTypeDescription
resetinputGlobal reset
clkinputGlobal clock
idmdataiinputData bus from IDATA memory
t0inputTimer 0 input
t1inputTimer 1 input
gate0inputTimer 0 gate input
gate1inputTimer 1 gate input
rxd0iinputSerial receiver input 0
capture0inputTimer 2 capture 0 line
capture1inputTimer 2 capture 1 line
capture2inputTimer 2 capture 2 line
capture3inputTimer 2 capture 3 line
t2inputTimer 2 clock line
t2exinputTimer 2 control
scliinputMaster/Slave I2C clock line input
sdaiinputMaster/Slave I2C data input
xdmdataiinputData bus from EDATA Memory
xdmreadyinputEDATA memory data ready
int0inputExternal interrupt 0
int1inputExternal interrupt 1
prgdataiinputData bus from CODE Memory
prgreadyinputCODE memory data ready
sfrdataiinputData bus from user SFR"s
tdiinputDoCDTM TAP data input
tckinputDoCDTM TAP clock input
tmsinputDoCDTM mode select input
port0iinputPort 0 input
port1iinputPort 1 input
port2iinputPort 2 input
port3iinputPort 3 input
rtcclkinputRTC clock input
rtcrstinputRTC reset input
rxd1iinputSerial receiver input 1
mosiinputSPI Master Output - Slave input
misoinputSPI Master input - Slave output
ssinputSPI slave select
sckinputSPI clock line
idmdataooutputData bus for IDATA memory
idmaddroutputIDATA Memory address bus
idmoeoutputInternal data memory output enable
idmweoutputInternal data memory write enable
rxd0ooutputSerial receiver output 0
txd0outputSerial transmitter output 0
sclooutputMaster/Slave I2C clock output
sclhsoutputHigh speed Master I2C clock line
sdaooutputMaster/Slave I2C data output
xdmdataooutputData bus for EDATA memories
xdmdatazoutputTurn EDATA bus into "Z" state
xdmaddroutputAddress bus for EDATA memory
xdmbeoutputEDATA data bus byte enable
xdmrdoutputExtended data memory read
xdmwroutputExtended data memory write
xdmceoutputExtended data memory chip enable
prgdataooutputData bus for CODE memory
prgdatazoutputTurn CODE bus into "Z" state
prgaddroutputCODE memory address bus
prgbeoutputCODE data bus byte enable
prgrdoutputCODE memory read
prgwroutputCODE memory write
sfrdataooutputData bus for user SFR"s
sfrraddroutputRead address bus for user SFR"s
sfrwaddroutputWrite address bus for user SFR"s
sfroeoutputUser SFR"s read enable
sfrweoutputUser SFR"s write enable
tdooutputDoCDTM TAP data output
rtckoutputDoCDTM return clock line
debugacsoutputDoCDTM accessing data
coderunoutputCPU is executing an instruction
port0ooutputPort 0 output
port1ooutputPort 1 output
port2ooutputPort 2 output
port3ooutputPort 3 output
stopoutputStop mode indicator
pmmoutputPower management mode indicator
rxd1ooutputSerial receiver output 1
txd1outputSerial transmitter line 1
sso (7:0)outputSlave Select outputs

Block Diagram

Control UnitPerforms the core synchronization and data flow control. This module is directly connected to Opcode Decoder and it manages the execution of all microcontroller tasks.
Opcode DecoderPerforms an opcode decoding instruction and control functions for all other blocks.
REGFILEContains complete set of 80251 dedicated: 8-bit {R0, R1, ..., R15} registers, 16-bit {WR0, WR2, ..., WR30} and 32-bit {DR0, DR4, ..., DR28, DR56, DR60} registers.
Internal Data Memory InterfaceInternal Data Memory interface controls access into the whole 32kB of IDATA memory. It contains 16-bit Stack Pointer (SP) register and related logic. It is fully configurable from 1 kB to 32 kB.
idmdatai
idmdatao
idmaddr
idmoe
idmwe
TimersSystem timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.
t0
t1
gate0
gate1
UART0Universal Asynchronous Receiver and Transmitter module is full duplex, which means, that it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of the second byte, before the previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in system).
rxd0i
rxd0o
txd0
Compare Capture UnitThe compare/capture/reload unit is one of the most powerful peripheral units of the core. It can be used for all kinds of digital signal generation and event capturing, such as pulse generation, pulse width modulation, measurements etc.
capture0
capture1
capture2
capture3
Timer 2Timer 2 - Second system timer module contains one 16-bit configurable timer: Timer 2 (TH2, TL2), capture registers (RLDH, RLDL) and Timer 2 Mode (T2MOD) register. It can work as a 16-bit timer / counter, 16-bit auto-reload timer / counter. It also supports compare capture unit (if present in the system). It can be used as clock source for UART0.
t2
t2ex
Slave I2C UnitI2C bus controller is a Slave module. The core incorporates all features required by I2C specification. It works as a slave transmitter/receiver, depending on working mode, determined by a master device. The I2C controller supports all transmission modes: Standard, Fast, Fast+ and High Speed up to 3400 kB/s.
Master I2C UnitI2C bus controller is a Master module. The core incorporates all features required by I2C specification. It supports both 7-bit and 10-bit addressing modes on the I2C bus and works as a master transmitter and receiver. It can be programmed to operate with arbitration and clock synchronization, to allow it to operate in multi-master systems. Built-in timer enables operation within wide range of the input frequencies. The timer allows to achieve any non-standard clock frequency. The I2C controller supports all transmission modes: Standard, Fast, Fast+ and High Speed up to 3400 kB/s.
scli
sdai
sclo
sclhs
sdao
EDATA Memory InterfaceContains memory access related registers. It performs the Extended Data Memory (EDATA) addressing and data transfers. EDATA read/write cycle length can be programmed by user. EDATA covers also XDATA space from 80C51. This feature is called EDATA Memory Wait States and allows core to work with different speed memories. It is fully configurable. It works with synchronous or asynchronous memories.
xdmdatai
xdmready
xdmdatao
xdmdataz
xdmaddr
xdmbe
xdmrd
xdmwr
xdmce
Interrupt ControllerFour Levels interrupt control module is responsible for the interrupt manage system, for external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IPH, IPL) and (TCON) registers. Its upgraded version can be extended by extra user's dedicated interrupt sources. Interrupt vectors locations and spacing are fully configurable.
int0
int1
Program Memory InterfaceContains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory (CODE) can be also written. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait States, and allows core to work with different speed program memories. It works with synchronous or asynchronous memories.
prgdatai
prgready
prgdatao
prgdataz
prgaddr
prgbe
prgrd
prgwr
SFRs InterfaceSpecial Function Registers interface - controls access to the special registers. It contains standard and used defined registers and related logic. All SFR registers are bit addressable. User defined external devices can be quickly accessed (read, written or modified), by the use of direct addressing mode instructions.
sfrdatai
sfrdatao
sfrraddr
sfrwaddr
sfroe
sfrwe
DoCDTM Debug UnitIt is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external data, program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, REGFILE and also on SFRs. Hardware breakpoint is executed, if any write/read occurrs at particular address, with certain data pattern or without pattern. Two additional pins - CODERUN and DEBUGACS, indicate the sate of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCDTM debugger. The DoCDTM system includes JTAG interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
tdi
tck
tms
tdo
rtck
debugacs
coderun
I/O portsBlock contains 8051 general purpose I/O ports. Each of ports pin can be read/write as a single bit or as a 8-bit bus P0, P1, P2, P3
port0i
port1i
port2i
port3i
port0o
port1o
port2o
port3o
Power Management UnitPower Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It's highly desirable, when microcontroller is planned to be used in portable and power critical applications.
stop
pmm
DRTCThe DRTC provides a Real Time Clock Calendar storing current time in Unix epoch format. The Unix epoch (called also POSIX time, Unix timestamp or Unix time) is the number of seconds that have elapsed since 1st January 1970 midnight UTC/GMT, not counting leap seconds (in ISO 8601: 1970-01-01T00:00:00Z). Many systems store epoch dates as a signed 32-bit integer, which might cause problems on 19th January 2038 (0x7FFFFFFF known as the Year 2038 problem). The DRTC has no such problem since its time is stored as unsigned 32-bit integer allowing correct work until 0xFFFFFFFF which is 07/Feb/2106. Additionally it can be extended to hold later future time.
rtcclk
rtcrst
ALUArithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic like arithmetic unit, logic unit, multiplier and divider.
Floating Point Math UnitFPMU contains floating arithmetic point xIEEE-754, compliant instructions (C float, int, long int types supported). It is used to execute single precision floating point operations such as: addition, subtraction, multiplication, division, square root, comparison absolute value of number and change of sign. Basing on specialized CORDIC algorithm, full set of trigonometric operations are also allowed: sine, cosine, tangent, arctangent. It also has built-in integer to floating point and vice versa conversion instructions. FPU supports single precision real numbers, 16-bit and 32-bit signed integers. This unit has included standard software interface, which enables easy usage and interfacing with user's C/ASM written programs.
MDU32 - 32-bit Multiply Divide UnitIt is a fixed point, fast 16-bit and 32-bit multiplication and division unit. It supports unsigned and 2's complement signed integer operands. The MDU32 is controlled by dedicated direct memory access module (called DMA). All arguments and result registers, are automatically read and written back by internal DMA. This unit has included standard software interface, which allows easy usage and interfacing with user C/ASM written programs. This module is a modern replacement for older MDU.
UART1Universal Asynchronous Receiver and Transmitter module is full duplex - it can transmit and receive concurrently. It includes Serial Configuration register (SCON1), serial receiver and transmitter buffer (SBUF1) registers. Its receiver is double-buffered, which means, it can commence reception of a second byte before the previously received byte has been read from the receive register. Writing to SBUF1, loads the transmit register and reading SBUF1, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART1 is synchronized by Timer 1.
rxd1i
rxd1o
txd1
Watchdog TimerThe watchdog timer is a 27-bit counter which is incremented in every system clock periods (CLK pin). It performs system protection against software upsets.
SPI UnitIt is a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communication in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough, to interface directly with numerous standard product peripherals, from several manufacturers. Data transfer rate up to CLK/4. Clock control logic allows to select the clock polarity and to choose the two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included, to support interprocessor communications. A write-collision detector indicates, when an attempt is made, to write data to the serial shift register, while the transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers, if more than one SPI device simultaneously attempts to become bus master.
mosi
miso
ss
sck
sso (7:0)
reset
clk
SFR bus Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture.
Data bus Internal data bus
SFR data bus 8-bit Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture.
Internal data bus 8-bit internal data bus

Units

Control Unit
Performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and it manages the execution of all microcontroller tasks.
Opcode Decoder
Performs an opcode decoding instruction and control functions for all other blocks.
REGFILE
Contains complete set of 80251 dedicated: 8-bit {R0, R1, ..., R15} registers, 16-bit {WR0, WR2, ..., WR30} and 32-bit {DR0, DR4, ..., DR28, DR56, DR60} registers.

Internal Data Memory Interface
Internal Data Memory interface controls access into the whole 32kB of IDATA memory. It contains 16-bit Stack Pointer (SP) register and related logic. It is fully configurable from 1 kB to 32 kB.
Timers
System timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.
UART0
Universal Asynchronous Receiver and Transmitter module is full duplex, which means, that it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of the second byte, before the previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in system).

Compare Capture Unit
The compare/capture/reload unit is one of the most powerful peripheral units of the core. It can be used for all kinds of digital signal generation and event capturing, such as pulse generation, pulse width modulation, measurements etc.
Timer 2
Timer 2 - Second system timer module contains one 16-bit configurable timer: Timer 2 (TH2, TL2), capture registers (RLDH, RLDL) and Timer 2 Mode (T2MOD) register. It can work as a 16-bit timer / counter, 16-bit auto-reload timer / counter. It also supports compare capture unit (if present in the system). It can be used as clock source for UART0.
Slave I2C Unit
I2C bus controller is a Slave module. The core incorporates all features required by I2C specification. It works as a slave transmitter/receiver, depending on working mode, determined by a master device. The I2C controller supports all transmission modes: Standard, Fast, Fast+ and High Speed up to 3400 kB/s.

Master I2C Unit
I2C bus controller is a Master module. The core incorporates all features required by I2C specification. It supports both 7-bit and 10-bit addressing modes on the I2C bus and works as a master transmitter and receiver. It can be programmed to operate with arbitration and clock synchronization, to allow it to operate in multi-master systems. Built-in timer enables operation within wide range of the input frequencies. The timer allows to achieve any non-standard clock frequency. The I2C controller supports all transmission modes: Standard, Fast, Fast+ and High Speed up to 3400 kB/s.
EDATA Memory Interface
Contains memory access related registers. It performs the Extended Data Memory (EDATA) addressing and data transfers. EDATA read/write cycle length can be programmed by user. EDATA covers also XDATA space from 80C51. This feature is called EDATA Memory Wait States and allows core to work with different speed memories. It is fully configurable. It works with synchronous or asynchronous memories.
Interrupt Controller
Four Levels interrupt control module is responsible for the interrupt manage system, for external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IPH, IPL) and (TCON) registers. Its upgraded version can be extended by extra user's dedicated interrupt sources. Interrupt vectors locations and spacing are fully configurable.

Program Memory Interface
Contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory (CODE) can be also written. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait States, and allows core to work with different speed program memories. It works with synchronous or asynchronous memories.
SFRs Interface
Special Function Registers interface - controls access to the special registers. It contains standard and used defined registers and related logic. All SFR registers are bit addressable. User defined external devices can be quickly accessed (read, written or modified), by the use of direct addressing mode instructions.
DoCDTM Debug Unit
It is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external data, program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, REGFILE and also on SFRs. Hardware breakpoint is executed, if any write/read occurrs at particular address, with certain data pattern or without pattern. Two additional pins - CODERUN and DEBUGACS, indicate the sate of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCDTM debugger. The DoCDTM system includes JTAG interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.

I/O ports
Block contains 8051 general purpose I/O ports. Each of ports pin can be read/write as a single bit or as a 8-bit bus P0, P1, P2, P3
Power Management Unit
Power Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It's highly desirable, when microcontroller is planned to be used in portable and power critical applications.
DRTC
The DRTC provides a Real Time Clock Calendar storing current time in Unix epoch format. The Unix epoch (called also POSIX time, Unix timestamp or Unix time) is the number of seconds that have elapsed since 1st January 1970 midnight UTC/GMT, not counting leap seconds (in ISO 8601: 1970-01-01T00:00:00Z). Many systems store epoch dates as a signed 32-bit integer, which might cause problems on 19th January 2038 (0x7FFFFFFF known as the Year 2038 problem). The DRTC has no such problem since its time is stored as unsigned 32-bit integer allowing correct work until 0xFFFFFFFF which is 07/Feb/2106. Additionally it can be extended to hold later future time.

ALU
Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic like arithmetic unit, logic unit, multiplier and divider.
Floating Point Math Unit
FPMU contains floating arithmetic point xIEEE-754, compliant instructions (C float, int, long int types supported). It is used to execute single precision floating point operations such as: addition, subtraction, multiplication, division, square root, comparison absolute value of number and change of sign. Basing on specialized CORDIC algorithm, full set of trigonometric operations are also allowed: sine, cosine, tangent, arctangent. It also has built-in integer to floating point and vice versa conversion instructions. FPU supports single precision real numbers, 16-bit and 32-bit signed integers. This unit has included standard software interface, which enables easy usage and interfacing with user's C/ASM written programs.
MDU32 - 32-bit Multiply Divide Unit
It is a fixed point, fast 16-bit and 32-bit multiplication and division unit. It supports unsigned and 2's complement signed integer operands. The MDU32 is controlled by dedicated direct memory access module (called DMA). All arguments and result registers, are automatically read and written back by internal DMA. This unit has included standard software interface, which allows easy usage and interfacing with user C/ASM written programs. This module is a modern replacement for older MDU.

UART1
Universal Asynchronous Receiver and Transmitter module is full duplex - it can transmit and receive concurrently. It includes Serial Configuration register (SCON1), serial receiver and transmitter buffer (SBUF1) registers. Its receiver is double-buffered, which means, it can commence reception of a second byte before the previously received byte has been read from the receive register. Writing to SBUF1, loads the transmit register and reading SBUF1, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART1 is synchronized by Timer 1.
Watchdog Timer
The watchdog timer is a 27-bit counter which is incremented in every system clock periods (CLK pin). It performs system protection against software upsets.
SPI Unit
It is a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communication in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough, to interface directly with numerous standard product peripherals, from several manufacturers. Data transfer rate up to CLK/4. Clock control logic allows to select the clock polarity and to choose the two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included, to support interprocessor communications. A write-collision detector indicates, when an attempt is made, to write data to the serial shift register, while the transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers, if more than one SPI device simultaneously attempts to become bus master.