Digital Core Design

The Power of Intellectual Property

DQ8051XP

Revolutionary Quad-Pipelined Ultra High Performance Microcontroller

The DQ8051XP is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller, designed to operate with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management PMU unit. The DQ8051XP soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. The DQ8051 has a built-in configurable DoCD-JTAG on-chip debugger, supporting Keil µVision development platform and standalone DoCD debug software. Dhrystone 2.1 benchmark program runs from 26.67 to 29.01 times faster than the original 80C51 at the same frequency. This performance can also be exploited to great advantage in low power applications, where the core can be clocked over ten times slower than the original implementation, withno performance penalty. The DQ8051XP is fully customizable - it is delivered in the exact configuration to meet your requirements. There is no need to pay extra for not used features and wasted silicon.

The DQ8051XP is delivered with fully automated testbench and complete set of tests, allowing easy package validation, at each stage of SoC design flow.

Each of DCD's 8051 cores has a built-in support for DCD's Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of the microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. More details about DCD's on-chip debugger


Family summary

 

Design Dhry
speed
on-chip
CODE
RAM/ROM
off-chip
CODE
CODE
write
IDATA
space
XDATA
space
XDATA,
CODE
wait states
DoCDTM PMU Interrupt
sources
DPTR Timers UART IO Ports Compare/
Capture
Watchdog MDU
MDU32
DI2CM DI2CS DSPI DFPMU DMAC DCAN
DQ80251 75.08 8M 8M + 1k-32k 8M + + +  15 1 3 2 4 + + + + + + + + +
DQ8051CPU 28.40 64k/64k 64k/8M + 256 16M + + +  2 2 - - - - - - - - - - - -
DQ8051 29.01 64k/64k 64k/8M + 256 16M + + +  5 2 2 1 4 - - - - - - - - -
DQ8051XP 29.01 64k/64k 64k/8M + 256 16M + + + 15 2 3 2 4 + + + + + + + + +
DP8051CPU 15.36 64k/64k 64k/8M + 256 16M + + +  2 1 - - - - - - - - - - - -
DP8051 15.36 64k/64k 64k/8M + 256 16M + + +  5 1 2 1 4 - - - - - - - - -
DP8051XP 15.55 64k/64k 64k/8M + 256 16M + + + 15 2 3 2 4 + + + + + + + + +
DP80C51 11.46 64k/64k 64k + 256 64k + + +  5 1 2 1 4 - - - - - - - - -
DT8051 8.11 64k/64k 64k + 256 64k - + + 11 1 2 1 1 - - - - - - - - -

The main features of each DCD's DQ8051, DQ80251, DP8051, DP80C51, DT8051 family member have been summarized in the table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and request the core modifications.

Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

Implementation
device
Speed
grade
Minimum
area
Top
frequency
0,35 um   typical   21600 gates 70 MHz
0,25 um typical 20800 gates 120 MHz
0,18 um typical 19600 gates 170 MHz
0,13 um typical 20100 gates 250 MHz
0,09 um typical 18900 gates 430 MHz

DQ8051XP core area and performance in ASIC devices - results given for working system   with two DPTRs and connected 256B IDM, 8kB CODE and 2kB SXDM memories. All CPU features and Peripherals except MAC and USB 2.0 controller have been included.  DoCD JTAG debugger increases core size by approximately 2 100 gates.  

Implementation
device
Speed
grade
Utilized Area
[gates]
Top
frequency
SPARTAN-6 -3 3550 LUT 55 MHz
VIRTEX-4 -12 3400 Slices 70 MHz
VIRTEX-5 -3 3200 LUT 100 MHz
VIRTEX-6 -3 3200 LUT 115 MHz

DQ8051XP core area and performance in XILINX devices - results given for working system,   with two DPTRs and connected 256B IDM, 8kB CODE and 2kB SXDM memories. All CPU features and Peripherals (except MAC and USB 2.0 controller) have been included. 

Implementation
device
Speed
grade
Utilized Area
[gates]
Top
frequency
CYCLONE-II -6 5350 LC 40 MHz
CYCLONE-III -6 5350 LC 50 MHz
CYCLONE-IV GX -6 5350 LC 50 MHz
STRATIX-II -3 3550 LUT 70 MHz
STRATIX-III -2 3550 LUT 100 MHz
STRATIX-IV -1 3550 LUT 90 MHz
STRATIX-V -2 3550 LUT 90 MHz

DQ8051XP core area and performance in ALTERA devices - results given for working system, with two DPTRs and connected 256B IDM, 8kB CODE and 2kB SXDM memories. All CPU features and Peripherals (except MAC and USB 2.0 controller) have been included. 


CPU Features


Symbol

 reset
 clk
 rxd1i
rxd1o 
txd1 
 t0
 t1
 gate0
 gate1
 rxd0i
rxd0o 
txd0 
 t2
 t2ex
 capture0
 capture1
 capture2
 capture3
 xdatai
 xdatardy
xaddress 
xdatao 
xdataz 
xdatawr 
xdatard 
 sxdmdatai
sxdmaddr 
sxdmdatao 
sxdmwe 
sxdmoe 
 scli
 scli
sclo 
sclhs 
sdao 
 prgdatai
 prgrdy
prgaddr 
prgdatao 
prgdataz 
prgrd 
prgwr 
 port0i
 port1i
 port2i
 port3i
port0o 
port1o 
port2o 
port3o 
stop 
pmm 
 int0
 int1
 int2
 int3
 int4
 int5
 int6
 idmdatai
idmaddr 
idmdatao 
idmwe 
idmoe 
 sfrdatai
sfraddr 
sfrdatao 
sfrwe 
sfroe 
 tdi
 tck
 tms
tdo 
rtck 
 mosi
 miso
 ss
 sck
sso (7:0) 
 rxclk
 rxdv
 rxer
 rxdata (3:0)
 qmr (7:0)
 txclk
 crs
 col
 qmt (7:0)
 mdi
dmr (7:0) 
waddrmr (10:0) 
raddrmr (10:0) 
enrmr 
enwmr 
txdata (3:0) 
txen 
txer 
dmt (7:0) 
waddrmt (10:0) 
raddrmt (10:0) 
enrmt 
enwmt 
mdc 
mdo 
mdoe 
 utmiclk
 utmilinestate (1:0)
 utmidatai (7:0)
 utmirxvalid
 utmirxactive
 utmirxerror
 utmitxready
 sramdataia (7:0)
 sramdataib (7:0)
utmiopmode (1:0) 
utmidatao (7:0) 
utmitxvalid 
utmisuspendm 
utmixcvrselect 
utmitermselect 
sramaddra (13:0) 
sramaddrb (13:0) 
sramdataoa (7:0) 
sramdataob (13:0) 
sramwea 
sramweb 
 rtcclk
 rtcrst

Pins description

PinTypeDescription
resetinputGlobal reset
clkinputGlobal clock
rxd1iinputSerial receiver input 1
t0inputTimer 0 input
t1inputTimer 1 input
gate0inputTimer 0 gate input
gate1inputTimer 1 gate input
rxd0iinputSerial receiver input 0
t2inputTimer 2 clock line
t2exinputTimer 2 control line
capture0inputTimer 2 capture 0 line
capture1inputTimer 2 capture 1 line
capture2inputTimer 2 capture 2 line
capture3inputTimer 2 capture 3 line
xdataiinputExternal Data Memory input bus
xdatardyinputExternal Data memory ready
sxdmdataiinputSynchronous External Data Memory input bus
scliinputMaster/Slave I2C clock line input
scliinputMaster/Slave I2C data input
prgdataiinputProgram memory data input bus
prgrdyinputProgram memory ready
port0iinputPort 0 input
port1iinputPort 1 input
port2iinputPort 2 input
port3iinputPort 3 input
int0inputExternal interrupt 0
int1inputExternal interrupt 1
int2inputExternal interrupt 2
int3inputExternal interrupt 3
int4inputExternal interrupt 4
int5inputExternal interrupt 5
int6inputExternal interrupt 6
idmdataiinputInternal Data Memory input bus
sfrdataiinputData bus from user SFRs
tdiinputDoCDTM TAP data input
tckinputDoCDTM TAP clock line
tmsinputDoCDTM TAP mode select
mosiinputSPI Master Output - Slave input
misoinputSPI Master input - Slave output
ssinputSPI slave select
sckinputSPI clock line
rxclkinputEthernet receive clock
rxdvinputEthernet receive data valid
rxerinputEthernet receive error
rxdata (3:0)inputEthernet receive data
qmr (7:0)inputRX DPRAM data output
txclkinputEthernet transmit clock
crsinputEthernet carrier sense
colinputEthernet collision detection
qmt (7:0)inputTX DPRAM data output
mdiinputManagement data input
utmiclkinputUSB clock
utmilinestate (1:0)inputUSB line state
utmidatai (7:0)inputUSB parallel data input bus
utmirxvalidinputUSB receive valid
utmirxactiveinputUSB receive active
utmirxerrorinputUSB receive error
utmitxreadyinputUSB transmit ready
sramdataia (7:0)inputSRAM port A data input bus
sramdataib (7:0)inputSRAM port B data input bus
rtcclkinputRTC clock input
rtcrstinputRTC reset input
rxd1ooutputSerial receiver output 1
txd1outputSerial transmitter line 1
rxd0ooutputSerial receiver output 0
txd0outputSerial transmitter output 0
xaddressoutputExternal Data Memory address bus
xdataooutputExternal Data Memory output bus
xdatazoutputTurns xdata bus into "Z" state
xdatawroutputExternal Data memory write
xdatardoutputExternal Data memory read
sxdmaddroutputSynchronous External Data Memory address bus
sxdmdataooutputSynchronous External Data Memory output bus
sxdmweoutputSynchronous External Data Memory write enable
sxdmoeoutputSynchronous External Data Memory output enable
sclooutputMaster/Slave I2C clock output
sclhsoutputHigh speed Master I2C clock line
sdaooutputMaster/Slave I2C data output
prgaddroutputProgram memory address bus
prgdataooutputProgram memory data output bus
prgdatazoutputTurns prgdatao bus into "Z" state
prgrdoutputProgram memory read
prgwroutputProgram memory write
port0ooutputPort 0 output
port1ooutputPort 1 output
port2ooutputPort 2 output
port3ooutputPort 3 output
stopoutputStop mode indicator
pmmoutputPower management mode indicator
idmaddroutputInternal Data Memory address bus
idmdataooutputInternal Data Memory output bus
idmweoutputInternal Data Memory write enable
idmoeoutputInternal Data Memory output enable
sfraddroutputUser SFRs address bus
sfrdataooutputData bus for user SFRs
sfrweoutputUser SFRs write enable
sfroeoutputUser SFRs output enable
tdooutputDoCDTM TAP data output
rtckoutputDoCDTM return clock
sso (7:0)outputSlave Select outputs
dmr (7:0)outputRX DPRAM data input
waddrmr (10:0)outputRX DPRAM write address
raddrmr (10:0)outputRX DPRAM read address
enrmroutputRX DPRAM read enable
enwmroutputRX DPRAM write enable
txdata (3:0)outputEthernet transmit data
txenoutputEthernet transmit enable
txeroutputEthernet transmit error
dmt (7:0)outputTX DPRAM data input
waddrmt (10:0)outputTX DPRAM write address
raddrmt (10:0)outputTX DPRAM read address
enrmtoutputTX DPRAM read enable
enwmtoutputTX DPRAM write enable
mdcoutputManagement clock
mdooutputManagement data output
mdoeoutputManagement data output enable
utmiopmode (1:0)outputUSB operational mode
utmidatao (7:0)outputUSB parallel data output bus
utmitxvalidoutputUSB transmit valid
utmisuspendmoutputUSB suspend
utmixcvrselectoutputUSB transceiver select
utmitermselectoutputUSB termination select
sramaddra (13:0)outputSRAM port A address bus
sramaddrb (13:0)outputSRAM port B address bus
sramdataoa (7:0)outputSRAM port A data output bus
sramdataob (13:0)outputSRAM port B data output bus
sramweaoutputSRAM port A write enable
sramweboutputSRAM port B write enable

Block Diagram

Opcode decoderPerforms an opcode decoding instruction and control functions for all other blocks.
Control UnitIt performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and it manages the execution of all microcontroller tasks.
UART1Universal Asynchronous Receiver and Transmitter module. It is full duplex, which means, that it can transmit and receive concurrently. Includes Serial Configuration register (SCON1), serial receiver and transmitter buffer (SBUF1) registers. Its receiver is double-buffered, meaning, it can commence reception of a second byte, before the previously received byte has been read from the receive register. Writing to SBUF1, loads the transmit register and reading SBUF1, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART1 is synchronized by Timer1.
rxd1i
rxd1o
txd1
TimersSystem timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.
t0
t1
gate0
gate1
UART0Universal Asynchronous Receiver and Transmitter module is full duplex, which means, that it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of the second byte, before the previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in system).
rxd0i
rxd0o
txd0
Timer 2Timer 2 - Second system timer module - contains one 16-bit configurable timer: Timer 2 (TH2, TL2); capture registers (RLDH, RLDL) and Timer 2 Mode (T2MOD) register. It can work as a 16-bit timer / counter, 16-bit auto-reload timer / counter. It also supports compare capture unit if it is presented in the system. It can be used as clock source for UART0.
t2
t2ex
Compare Capture UnitThe compare/capture/reload unit is one of the most powerful peripheral units of the core. It can be used for all kinds of digital signal generation and event capturing, such as pulse generation, pulse width modulation, measurements etc.
capture0
capture1
capture2
capture3
External Data Memory InterfaceIt contains memory access related registers, such as Data Pointer High (DPH), Data Pointer Low (DPL), Data Page Pointer (DPP), MOVX @Ri address register (MXAX) and STRETCH registers. It performs the memory addressing and data transfers. It also allows applications software to access up to 16 MB of external data memory. The DPP register is used for segments swapping. STRETCH register allows flexible timing management, while accessing different speed system devices, by programming XDATAWR and XDATARD pulse width between 1 and 8 clock periods.
xdatai
xaddress
xdatao
xdataz
xdatardy
xdatawr
xdatard
SXDM InterfaceSynchronous eXternal Data Memory (SXDM) Interface contains XDATA memory access related logic, allowing fast access to synchronous memory devices. It performs the external Data Memory addressing and data transfers. This memory can be used to store large variables, frequently accessed by CPU, improving overall performance of application.
sxdmdatai
sxdmaddr
sxdmdatao
sxdmwe
sxdmoe
Master I2C Bus ControllerThe Master I2C Bus Controller core incorporates all features required by I2C specification. Supports both 7-bit and 10-bit addressing modes, on the I2C bus. It works as a master transmitter and receiver. It can be programmed to operate with arbitration and clock synchronization, letting it to operate in multi-master systems. Built-in timer allows operation from wide range of the input frequencies. The timer allows to achieve any non-standard clock frequency. The I2C controller supports all transmission modes: Standard, Fast, Fast+ and High Speed - up to 3400 kB/s.
scli
scli
sclo
sclhs
sdao
Slave I2C Bus ControllerThe Slave I2C bus controller core incorporates all features required by I2C specification. It works as a slave transmitter/receiver, depending on working mode determined by a master device. The I2C controller supports all transmission modes: Standard, Fast, Fast+ and High Speed up to 3400 kB/s.
Program Memory InterfaceProgram Memory Interface contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader, to load new program into ROM, RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCD™ module.
prgdatai
prgaddr
prgdatao
prgdataz
prgrdy
prgrd
prgwr
I/O portsBlock contains 8051 general purpose I/O ports. Each of ports pin can be read/write as a single bit or as a 8-bit bus P0, P1, P2, P3
port0i
port1i
port2i
port3i
port0o
port1o
port2o
port3o
Power Management UnitPower Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It's highly desirable, when microcontroller is planned to be used in portable and power critical applications.
stop
pmm
Extended Interrupt ControllerInterrupt Controller module is responsible for the interrupt managing system, for the external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IP), Extended Interrupt Enable (EIE), Extended Interrupt priority (EIP) and (TCON) registers.
int0
int1
int2
int3
int4
int5
int6
Internal Data Memory InterfaceInterface controls access to the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.
idmdatai
idmaddr
idmdatao
idmwe
idmoe
SFR InterfaceSpecial Function Registers interface - controls access to externally connected peripherals through SFR bus.
sfrdatai
sfraddr
sfrdatao
sfrwe
sfroe
MDU32 - 32-bit Multiply Divide UnitIt is a fixed point fast, 16-bit and 32-bit multiplication and division unit. It supports unsigned and 2,s complement signed integer operands. The MDU32 is controlled by dedicated direct memory access module (called DMA). All arguments and result registers are automatically read and written back by internal DMA. This unit has included standard software interface, that allows easy usage and interfacing with user C/ASM written programs. This module is a modern replacement for older MDU.
Floating Point Math UnitFPMU contains floating point arithmetic IEEE-754 compliant instructions (C float, int, long int types supported). It is used to execute single precision floating point operations such as: addition, subtraction, multiplication, division, square root, comparison absolute value of number and change of sign. Basing on specialized CORDIC algorithm, a full set of trigonometric operations are also allowed: sine, cosine, tangent, arctangent. It also has built-in integer to floating point and vice versa conversion instructions. FPU supports single precision real numbers, 16-bit and 32-bit signed integers. This unit has included standard software interface, that allows easy usage and interfacing with user's C/ASM written programs.
DoCDTM TTAG DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware watchpoints can be set and controlled on internal and external data memories and also on SFRs. Hardware watchpoints are executed, if any write/read occurs at particular address, with certain data pattern or without pattern. Two additional pins: CODERUN and DEBUGACS, indicate the state of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCDTM debugger. The DoCDTM system includes TTAG interface and complete set of tools, to communicate and work with core in real time debugging. It is built, as a scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
tdi
tck
tms
tdo
rtck
SPI UnitIt's a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included to support interprocessor communications. A write-collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers if more than one SPI devices simultaneously attempts to become bus master.
mosi
miso
ss
sck
sso (7:0)
Watchdog TimerThe watchdog timer is a 27-bit counter, which is incremented in every system clock period (CLK pin). It performs system protection against software upsets.
MAC - 10/100 Mb Media Access ControllerThe DMAC is hardware implementation of media access control protocol, defined by the IEEE standard. DMAC, in cooperation with external PHY device, enables network functionality in design. It is capable of transmitting and receiving Ethernet frames, to and from the network. Half and full duplex modes are supported at 10 and 100 Mbit/s speed. The DMAC provides static configuration of PHY IC. Design is technology independent and thus can be implemented in a variety of process technologies. This core strictly conforms to IEEE 802.3 standard.
rxclk
rxdv
rxer
rxdata (3:0)
qmr (7:0)
dmr (7:0)
waddrmr (10:0)
raddrmr (10:0)
enrmr
enwmr
txclk
crs
col
txdata (3:0)
txen
txer
qmt (7:0)
dmt (7:0)
waddrmt (10:0)
raddrmt (10:0)
enrmt
enwmt
mdc
mdi
mdo
mdoe
USB 2.0 Device ControllerThe USB 2.0 Device Controller is hardware implementation of full/high-speed peripheral controller that interfaces to UTMI bus transceiver. It contains the USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic. This controller is designed to support 12 Mb/s "Full Speed" (FS) and 480 Mb/s "High Speed" (HS) serial data transmission rates. This module strictly conforms to USB Specification v2.0.
utmiclk
utmilinestate (1:0)
utmidatai (7:0)
utmirxvalid
utmirxactive
utmirxerror
utmitxready
utmiopmode (1:0)
utmidatao (7:0)
utmitxvalid
utmisuspendm
utmixcvrselect
utmitermselect
sramdataia (7:0)
sramdataib (7:0)
sramaddra (13:0)
sramaddrb (13:0)
sramdataoa (7:0)
sramdataob (13:0)
sramwea
sramweb
ALUArithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic like arithmetic unit, logic unit, multiplier and divider.
DRTCThe DRTC provides a Real Time Clock Calendar storing current time in Unix epoch format. The Unix epoch (called also POSIX time, Unix timestamp or Unix time) is the number of seconds that have elapsed since 1st January 1970 midnight UTC/GMT, not counting leap seconds (in ISO 8601: 1970-01-01T00:00:00Z). Many systems store epoch dates as a signed 32-bit integer, which might cause problems on 19th January 2038 (0x7FFFFFFF known as the Year 2038 problem). The DRTC has no such problem since its time is stored as unsigned 32-bit integer allowing correct work until 0xFFFFFFFF which is 07/Feb/2106. Additionally it can be extended to hold later future time.
rtcclk
rtcrst
reset
clk
Internal data bus 8-bit internal data bus
SFR data bus 8-bit Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture.

Units

Opcode decoder
Performs an opcode decoding instruction and control functions for all other blocks.
Control Unit
It performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and it manages the execution of all microcontroller tasks.
UART1
Universal Asynchronous Receiver and Transmitter module. It is full duplex, which means, that it can transmit and receive concurrently. Includes Serial Configuration register (SCON1), serial receiver and transmitter buffer (SBUF1) registers. Its receiver is double-buffered, meaning, it can commence reception of a second byte, before the previously received byte has been read from the receive register. Writing to SBUF1, loads the transmit register and reading SBUF1, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART1 is synchronized by Timer1.

Timers
System timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.
UART0
Universal Asynchronous Receiver and Transmitter module is full duplex, which means, that it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of the second byte, before the previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in system).
Timer 2
Timer 2 - Second system timer module - contains one 16-bit configurable timer: Timer 2 (TH2, TL2); capture registers (RLDH, RLDL) and Timer 2 Mode (T2MOD) register. It can work as a 16-bit timer / counter, 16-bit auto-reload timer / counter. It also supports compare capture unit if it is presented in the system. It can be used as clock source for UART0.

Compare Capture Unit
The compare/capture/reload unit is one of the most powerful peripheral units of the core. It can be used for all kinds of digital signal generation and event capturing, such as pulse generation, pulse width modulation, measurements etc.
External Data Memory Interface
It contains memory access related registers, such as Data Pointer High (DPH), Data Pointer Low (DPL), Data Page Pointer (DPP), MOVX @Ri address register (MXAX) and STRETCH registers. It performs the memory addressing and data transfers. It also allows applications software to access up to 16 MB of external data memory. The DPP register is used for segments swapping. STRETCH register allows flexible timing management, while accessing different speed system devices, by programming XDATAWR and XDATARD pulse width between 1 and 8 clock periods.
SXDM Interface
Synchronous eXternal Data Memory (SXDM) Interface contains XDATA memory access related logic, allowing fast access to synchronous memory devices. It performs the external Data Memory addressing and data transfers. This memory can be used to store large variables, frequently accessed by CPU, improving overall performance of application.

Master I2C Bus Controller
The Master I2C Bus Controller core incorporates all features required by I2C specification. Supports both 7-bit and 10-bit addressing modes, on the I2C bus. It works as a master transmitter and receiver. It can be programmed to operate with arbitration and clock synchronization, letting it to operate in multi-master systems. Built-in timer allows operation from wide range of the input frequencies. The timer allows to achieve any non-standard clock frequency. The I2C controller supports all transmission modes: Standard, Fast, Fast+ and High Speed - up to 3400 kB/s.
Slave I2C Bus Controller
The Slave I2C bus controller core incorporates all features required by I2C specification. It works as a slave transmitter/receiver, depending on working mode determined by a master device. The I2C controller supports all transmission modes: Standard, Fast, Fast+ and High Speed up to 3400 kB/s.
Program Memory Interface
Program Memory Interface contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader, to load new program into ROM, RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCD™ module.

I/O ports
Block contains 8051 general purpose I/O ports. Each of ports pin can be read/write as a single bit or as a 8-bit bus P0, P1, P2, P3
Power Management Unit
Power Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It's highly desirable, when microcontroller is planned to be used in portable and power critical applications.
Extended Interrupt Controller
Interrupt Controller module is responsible for the interrupt managing system, for the external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IP), Extended Interrupt Enable (EIE), Extended Interrupt priority (EIP) and (TCON) registers.

Internal Data Memory Interface
Interface controls access to the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.
SFR Interface
Special Function Registers interface - controls access to externally connected peripherals through SFR bus.
MDU32 - 32-bit Multiply Divide Unit
It is a fixed point fast, 16-bit and 32-bit multiplication and division unit. It supports unsigned and 2,s complement signed integer operands. The MDU32 is controlled by dedicated direct memory access module (called DMA). All arguments and result registers are automatically read and written back by internal DMA. This unit has included standard software interface, that allows easy usage and interfacing with user C/ASM written programs. This module is a modern replacement for older MDU.

Floating Point Math Unit
FPMU contains floating point arithmetic IEEE-754 compliant instructions (C float, int, long int types supported). It is used to execute single precision floating point operations such as: addition, subtraction, multiplication, division, square root, comparison absolute value of number and change of sign. Basing on specialized CORDIC algorithm, a full set of trigonometric operations are also allowed: sine, cosine, tangent, arctangent. It also has built-in integer to floating point and vice versa conversion instructions. FPU supports single precision real numbers, 16-bit and 32-bit signed integers. This unit has included standard software interface, that allows easy usage and interfacing with user's C/ASM written programs.
DoCDTM TTAG
DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware watchpoints can be set and controlled on internal and external data memories and also on SFRs. Hardware watchpoints are executed, if any write/read occurs at particular address, with certain data pattern or without pattern. Two additional pins: CODERUN and DEBUGACS, indicate the state of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCDTM debugger. The DoCDTM system includes TTAG interface and complete set of tools, to communicate and work with core in real time debugging. It is built, as a scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
SPI Unit
It's a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included to support interprocessor communications. A write-collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers if more than one SPI devices simultaneously attempts to become bus master.

Watchdog Timer
The watchdog timer is a 27-bit counter, which is incremented in every system clock period (CLK pin). It performs system protection against software upsets.
MAC - 10/100 Mb Media Access Controller
The DMAC is hardware implementation of media access control protocol, defined by the IEEE standard. DMAC, in cooperation with external PHY device, enables network functionality in design. It is capable of transmitting and receiving Ethernet frames, to and from the network. Half and full duplex modes are supported at 10 and 100 Mbit/s speed. The DMAC provides static configuration of PHY IC. Design is technology independent and thus can be implemented in a variety of process technologies. This core strictly conforms to IEEE 802.3 standard.
USB 2.0 Device Controller
The USB 2.0 Device Controller is hardware implementation of full/high-speed peripheral controller that interfaces to UTMI bus transceiver. It contains the USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic. This controller is designed to support 12 Mb/s "Full Speed" (FS) and 480 Mb/s "High Speed" (HS) serial data transmission rates. This module strictly conforms to USB Specification v2.0.

ALU
Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic like arithmetic unit, logic unit, multiplier and divider.
DRTC
The DRTC provides a Real Time Clock Calendar storing current time in Unix epoch format. The Unix epoch (called also POSIX time, Unix timestamp or Unix time) is the number of seconds that have elapsed since 1st January 1970 midnight UTC/GMT, not counting leap seconds (in ISO 8601: 1970-01-01T00:00:00Z). Many systems store epoch dates as a signed 32-bit integer, which might cause problems on 19th January 2038 (0x7FFFFFFF known as the Year 2038 problem). The DRTC has no such problem since its time is stored as unsigned 32-bit integer allowing correct work until 0xFFFFFFFF which is 07/Feb/2106. Additionally it can be extended to hold later future time.