Digital Core Design

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DEEPROM

Serial EEPROM Controller

    The DEEPROM performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface. Its contents are accessible to the CPU in the same manner as a common SRAM memory, but require READY input to expand the time access. Our proprietary core allows to map serial EEPROM in processor memory space and control it as the parallel memory. The controller automatically sends all control instructions and read /write memory locations. As for the CPU, the EEPROM is connected to it through the DEEPROM. Moreover, it's visible and controlled as parallel SRAM with long access time. Our unique Core has been designed to operate with popular 25XXX SPI Serial EEPROMs (Atmel, Microchip).


    Key Features

    • Standard memory interface with ready control
    • Configurable SPI parameters
      • Serial clock prescaler
      • SPI mode
      • CS hold/setup
    • Updating bits in EEPROM status register
    • Simple interface allows easy connection to microcontrollers
    • Fully synthesizable, static design with no internal tri-states

    Applications

    Applcations requiring data storage in external non-voltile memories.


    Symbol

     rst
     clk
     addr (15:0)
     datai (7:0)
     wr
     rd
     cs
    datao (7:0) 
    ready 
     esi
    eso 
    eck 
    ecs 

    Pins description

    PinTypeDescription
    rstinputGlobal reset
    clkinputGlobal clock
    addr (15:0)inputMicrcprocessor address bus
    datai (7:0)inputData Bus input
    wrinputWrite signal
    rdinputRead input
    csinputChip select
    esiinputEEPROM serial data input
    datao (7:0)outputDatabus output
    readyoutputReady signal
    esooutputSerial data output
    eckoutputSerial clock
    ecsoutputEEPROM Chip Select

    Block Diagram

    Control UnitControl Unit manages execution of all commands sent via interface. Synchronizes internal data flow.
    CPU InterfaceThe CPU Interface manage bada exchange between CPU and DEEPROMCTRL. It allows parallel data to be written to and read from DEEPROMCTRL and transfered serial to/from external serial EEPROM Memory.
    addr (15:0)
    datai (7:0)
    datao (7:0)
    wr
    rd
    cs
    ready
    EEPOM InterfaceEEPROM interface manages serial data exchange between DEEPROMCTRL and external serial EEPROM.
    esi
    eso
    eck
    ecs
    rst
    clk
    Internal data bus 8-bit internal data bus

    Units

    Control Unit
    Control Unit manages execution of all commands sent via interface. Synchronizes internal data flow.
    CPU Interface
    The CPU Interface manage bada exchange between CPU and DEEPROMCTRL. It allows parallel data to be written to and read from DEEPROMCTRL and transfered serial to/from external serial EEPROM Memory.
    EEPOM Interface
    EEPROM interface manages serial data exchange between DEEPROMCTRL and external serial EEPROM.