Digital Core Design

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DSDRAM

SDRAM Controller

    The DSDRAM is an IP Core of a configurable SDRAM controller. Naturally, it is fully compliant to JEDEC PC100/133 standards. Our infallible soft Core can operate with any SDRAM memory device, in terms of size and required timing parameters. All access timing parameters - such as CAS latency, refresh interval etc. - can be easily programmed. Thanks to this useful feature, the DSDRAM can support different speed grades of SDRAM devices and different operating frequencies. The timing parameters can be simply set to the proper default values during synthesis time. DCD's IP Core is very small, efficient, static, fully synchronous design, with no internal tri-state buffers and signals.


    Key Features


    Symbol

     rst
     clk
     sddq
     address (23:0)
     datai (31:0)
     cs
     wr
     rd
     be (2:0)
    datao (31:0) 
    busy 

    Pins description

    PinTypeDescription
    rstinputGlobal reset
    clkinputGlobal clock
    sddqinputSDRAM databus
    address (23:0)inputProcessor address bus
    datai (31:0)inputData Bus input
    csinputChip select
    wrinputProcessor data write
    rdinputProcessor data read
    be (2:0)inputByte enable
    datao (31:0)outputProcessor data bus output
    busyoutputProcessor data busy

    Block Diagram

    STATE CONTROLLERState controller sends appropriate command to SDRAM memory, depend on selected controller mode and executable operation.
    SDRAM INTERFACESDRAM Interface performs the interface functions between DSDRAM internal blocks and SDRAM memory. It allows an easy core connection to the memory system.
    sddq
    ADDRESS GENERATORAddress generator transfers address from CPU side to suitable blocks, row and column of SDRAM memory side.
    CPU INTERFACECPU Interface performs the interface functions between DSDRAM internal blocks and microprocessor. It allows easy core connection to the microprocessor/microcontroller system.
    address (23:0)
    datai (31:0)
    datao (31:0)
    cs
    wr
    rd
    be (2:0)
    busy
    rst
    clk
    Internal data bus 8-bit internal data bus

    Units

    STATE CONTROLLER
    State controller sends appropriate command to SDRAM memory, depend on selected controller mode and executable operation.
    SDRAM INTERFACE
    SDRAM Interface performs the interface functions between DSDRAM internal blocks and SDRAM memory. It allows an easy core connection to the memory system.
    ADDRESS GENERATOR
    Address generator transfers address from CPU side to suitable blocks, row and column of SDRAM memory side.

    CPU INTERFACE
    CPU Interface performs the interface functions between DSDRAM internal blocks and microprocessor. It allows easy core connection to the microprocessor/microcontroller system.