The DSDRAM is an IP Core of a configurable SDRAM controller. Naturally, it is fully compliant to JEDEC PC100/133 standards. Our infallible soft Core can operate with any SDRAM memory device, in terms of size and required timing parameters. All access timing parameters - such as CAS latency, refresh interval etc. - can be easily programmed. Thanks to this useful feature, the DSDRAM can support different speed grades of SDRAM devices and different operating frequencies. The timing parameters can be simply set to the proper default values during synthesis time. DCD's IP Core is very small, efficient, static, fully synchronous design, with no internal tri-state buffers and signals.
- Supports any SDRAM discrete devices
- PC 66/100/133 SDRAM
- SDRAM from 16 Mbit to 1024 Mbit sizes
- Programmable data size
- Supports all burst lengths
- CAS latency
- Programmable access timing parameters
- Supports multiple external SDRAM banks
- Automatic refresh generation with programmable refresh intervals
- Self refreshing mode
- Fully synthesizable, static design with no internal tri-states
|address (23:0)||input||Processor address bus|
|datai (31:0)||input||Data Bus input|
|wr||input||Processor data write|
|rd||input||Processor data read|
|be (2:0)||input||Byte enable|
|datao (31:0)||output||Processor data bus output|
|busy||output||Processor data busy|
STATE CONTROLLERState controller sends appropriate command to SDRAM memory, depend on selected controller mode and executable operation.
SDRAM INTERFACESDRAM Interface performs the interface functions between DSDRAM internal blocks and SDRAM memory. It allows an easy core connection to the memory system.
ADDRESS GENERATORAddress generator transfers address from CPU side to suitable blocks, row and column of SDRAM memory side.
CPU INTERFACECPU Interface performs the interface functions between DSDRAM internal blocks and microprocessor. It allows easy core connection to the microprocessor/microcontroller system.