Digital Core Design

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D8259

Programmable Interrupt Controller

    The D8259 is a soft Core of Programmable Interrupt Controller. It is fully compatible with the 82C59A device. Our efficient IP core can manage up to 8-vectored priority interrupts for the processor. Moreover, you can also program it to cascade and gain up to 64 vectored interrupts. And if it's not enough, you can always get more than 64 vectored interrupts. Just program our IP Core to the Poll Command Mode. The D8259 can operate in all 82C59A modes and it supports all 82C59A features.
     

    The D8259 Package includes fully automated testbench. Thanks to complete set of tests, you can easily validate the whole package at each stage of SoC design flow. Same as all DCD's IP Cores, this one's got also a technology independent design, that can be implemented in a variety of process technologies.


    Performance

    Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.

    Implementation Logic Cells Frequency
    [MHz]
    CYCLONE-5 210 154
    CYCLONE-4 403 189
    CYCLONE-3 409 186
    CYCLONE-2 387 163
    CYCLONE 394 154
    ARRIA-5 213 336
    ARRIA-2 341 316
    STRATIX-5 213 357
    STRATIX-4 331 347
    STRATIX-3 344 365
    STRATIX-2 294 239
    STRATIX 394 164
    MAX-5 405 54
    MAX-2 405 107

    D8259 implementation results for ALTERA devices. All features have been included.

    Implementation Slices Frequency
    [MHz]
    ARTIX-7 128/267 320
    KINTEX-7 128/288 340
    ZYNQ 128/288 218
    SPARTAN-6 132/283 140
    SPARTAN-3 134/283 104
    VIRTEX-7 128/288 340
    VIRTEX-6 130260 231
    VIRTEX-5 130/272 247
    VIRTEX-4 130/252 203

    D8259 implementation results for XILINX devices. All features have been included. 


    Implementation Speed
    grade
    Utilized Area
    [LUT/PFU]
    Frequency
    [MHz]
    EC -5 394 / 125 114
    ECP -5 394 / 125 114
    XP -5 394 / 125 108

    D8259 implementation results for LATTICE devices. All features have been included. 

    Technology Optimization Gates Frequency
    [MHz]
    0.25 typical area 1800 120
    0.25 typical speed 2700 200

    D8259 implementation results for ASIC devices. All features have been included. 


    Key Features

    • 8 vectored priority interrupts
    • Up to sixty-four vectored priority interrupts with cascading
    • Support for all 82C59A modes features
      • MCS-80/85 and 8088/8086 processor modes
      • Fully nested mode and special fully nested mode
      • Special mask mode
      • Buffered mode
      • Pool command mode
      • Cascade mode with master or slave selection
      • Automatic end-of-interrupt mode
      • Specific and non-specific end-of-interrupt commands
      • Automatic and Specific Rotation
      • Edge and level triggered interrupt input modes
      • Reading of interrupt request register (IIR) and in-service register (ISR) through data bus
    • Fully synthesizable HDL Source Code
    • Static design and no internal tri-states

    Applications

    • Embedded microprocessor boards

    Symbol

     clk
     rst
     datai (7:0)
    datao (7:0) 
    dbe 
     casi (2:0)
     sp
    caso (2:0) 
    case 
    en 
     inta
    int 
     ir (6:0)
     rst
     a0
     wr
     cs
     rd

    Pins description

    PinTypeDescription
    clkinputGlobal clock
    rstinputGlobal reset
    datai (7:0)inputData bus input
    casi (2:0)inputCascade input lines
    spinputSlave program input
    intainputInterrupt acknowledge
    ir (6:0)inputInterrupt Request lines
    rstinputPower-up reset
    a0inputProcessor address line
    wrinputWrite strobe
    csinputChip select
    rdinputRead strobe
    datao (7:0)outputData Bus output
    dbeoutputData bus output enable
    caso (2:0)outputCascade output lines
    caseoutputCascade output enable
    enoutputBuffer transceiver enable
    intoutputInterrupt request output

    Block Diagram

    Data Bus Buffer8-bit buffer is used to interface the D8259 to the system bus.
    datai (7:0)
    datao (7:0)
    dbe
    Cascade ControllerThe Cascade Controller stores and compares Identifiers of all 8259 devices in the system. Block manages direction of CAS input/output buses, depending of device status: Master or Slave. When operating as a master the D8259 drives onto the CAS bus address of interrupting 8259 device, then the addressed 8259 slave, during the next one or two consecutive INTA pulses sends preprogrammed address of subroutine to the Data Bus.
    casi (2:0)
    caso (2:0)
    case
    en
    sp
    Control LogicControl Logic block checks for INTA pulses, which cause the D8259 to release vectoring information onto the Data Bus. Format of drive data depends on mode of operation. Control Logic also manages state of INT output.
    inta
    int
    In Service RegisterService Register stores information about interrupts that are being serviced.
    Interrupt Mask RegisterIMR register stores the information which interrupt request to be masked.
    Interrupt Request RegisterInterrupt Request Register stores information about states of all IR lines. It saves information about all interrupt requests that need to be serviced.
    ir (6:0)
    Priority ResolverPiority Resolver block resolves which interrupt request has the highest priority and will be served as first.
    Read / Write LogicThe Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the D8259. A \"low\" on the RD input tells the D8259 that the CPU is reading contents of IRR and ISR registers. On the other hand, a \"low\" on the WR input tells the D8254, that the CPU is writing a Command Words to D8259. Both RD and WR are qualified by CS; RD and WR are ignored unless the D8259 has been selected by holding CS low.
    rst
    a0
    wr
    cs
    rd
    clk
    rst
    Data Bus Virtual internal Data Bus

    Units

    Data Bus Buffer
    8-bit buffer is used to interface the D8259 to the system bus.
    Cascade Controller
    The Cascade Controller stores and compares Identifiers of all 8259 devices in the system. Block manages direction of CAS input/output buses, depending of device status: Master or Slave. When operating as a master the D8259 drives onto the CAS bus address of interrupting 8259 device, then the addressed 8259 slave, during the next one or two consecutive INTA pulses sends preprogrammed address of subroutine to the Data Bus.
    Control Logic
    Control Logic block checks for INTA pulses, which cause the D8259 to release vectoring information onto the Data Bus. Format of drive data depends on mode of operation. Control Logic also manages state of INT output.

    In Service Register
    Service Register stores information about interrupts that are being serviced.
    Interrupt Mask Register
    IMR register stores the information which interrupt request to be masked.
    Interrupt Request Register
    Interrupt Request Register stores information about states of all IR lines. It saves information about all interrupt requests that need to be serviced.

    Priority Resolver
    Piority Resolver block resolves which interrupt request has the highest priority and will be served as first.
    Read / Write Logic
    The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the D8259. A \"low\" on the RD input tells the D8259 that the CPU is reading contents of IRR and ISR registers. On the other hand, a \"low\" on the WR input tells the D8254, that the CPU is writing a Command Words to D8259. Both RD and WR are qualified by CS; RD and WR are ignored unless the D8259 has been selected by holding CS low.