Digital Core Design

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DBLCD32

LCD/TFT Controller

    The DCD’s DBLCD32 core is a fully configurable, universal LCD/TFT display controller. It supports a wide range of resolution and enables both, horizontal and vertical synchronization parameters setup. The display’s pixel clock can be generated by an internal pixel clock divider based on the bus clock, or delivered to the core by a dedicated pin. Additionally there is a possibility of using an externally generated pixel clock. Polarization of the generated pixel clock, as well as synchronization signals, is configurable. The DBLCD32 has a DMA capable master interface, which can be used to access a framebuffer placed directly in a system memory. Embedded DMA controller has configurable FIFO to store pixels data, which increases system throughput and performance. Transmission on the master interface is burst oriented and there is a possibility of defining the burst size limit. Data fetched by the DMA interface can be translated to 24-bits RGB signals, depending on the selected color mode. There are three standard color modes supported: 24-bits True Color, 16-bits(5-6-5) High Color and 8-bits index color mode. Additionally, a 32-bit True Color is also supported, but the MSB byte of each four byte word is ignored. In case of the Indexed Color Mode the DBLCD32 is equipped with pixel palette RAM which is used to translate each byte from the display buffer into 24-bit RGB output. There are two different formats of color palettes available. The core supports the page flipping mechanism, which enables the usage of multiple buffering totally without the tearing effect. There is also a set of programmable interrupts available related to both display synchronization and DMA status signals. The core is capable to work on both little and big endian systems. To increase the system performance and flexibility of usage, the DLBLCD32 can be configured in two possible optimization levels, to find a proper balance between a gate count and a critical path length.

     

     

    Key Features

    •   24-bit RGB interface,
    •   Configurable display resolution,
    •   Configurable horizontal sync length and blanking,
    •   Configurable vertical sync length and blanking,
    •   Configurable RGB signals polarization,
    •   Configurable pixel clock polarization,
    •   Internal pixel clock divider,
    •   Different pixel clock modes,
    •   DMA capable interface,
    •   Configurable DMA FIFO,
    •   Configurable burst size limit,
    •   AHB bus interface(32-bit)
    •   24-bit True Color mode support,
    •   16-bit (5-6-5) High Color mode support,
    •   8-bit Indexed Color mode support,
    •   32-bit True Color mode support (one byte ignored),
    •   Pixel palette RAM,
    •   Page flipping support,
    •   Programmable interrupts,
    •   Big and little - endian support,
    •   Two different optimization levels,
    •   Fully synthesizable, synchronous design.

     


    Performance

    Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.

    Device Slices/
    LUTS/Registers
    ahb_hclk/pxl_clko
    ARTIX 7 XC7A350T-3 254/425/308  162 MHz/81 MHz
    KINTEX 7 XC7K480T-3 252/523/308 174 MHz/87 MHz
    ZYNQ XC7Z045-3 265/524/308 195 MHz/97 MHz

    DBLCD32 implementation results for XILINX devices.
    Size optimized results. Pixel clock driven from the bus clock.

    Device Slices/
    LUTS/Registers
    ahb_hclk/pxl_clko
    ARTIX 7 XC7A350T-3 268/482/435 283 MHz/147 MHz
    KINTEX 7 XC7K480T-3 299/587/435 348 MHz/189 MHz
    ZYNQ XC7Z045-3 296/574/435 363 MHz/181 MHz

    DBLCD32 implementation results for XILINX devices.
    Speed optimized results. Pixel clock driven from the dedicated pin

    Device ALMS/
    Registers
    ahb_hclk/pxl_clko
    ARIA V 5AGXFB3 270 / 360 248 MHz/124 MHz
    CYCLONE V 5CEBA9 268 / 365 168 MHz/84 MHz
    STRATIX V 5SEE9H 267/ 365 398 MHz/199 MHz

    DBLCD32  implementation results for ALTERA devices.
    Size optimized results. Pixel clock driven from the bus clock.

    Device ALMS/
    Registers
    ahb_hclk/pxl_clko
    ARIA V 5AGXFB3 295  / 399 370 MHZ/200 MHz
    CYCLONE V 5CEBA9 297  / 408 223 MHz/114 MHz
    STRATIX V 5SEE9H 323 / 400 564 MHz/294 MHz

    DBLCD32  implementation results for ALTERA devices.
    Speed optimized results. Pixel clock driven from the dedicated pin.

    Technology
    /optimization
    Speed grade Area [gates]
    0.18u  typical 1850
    0.09u typical 1800

    DBLCD32  implementation results for ASIC devices.
    Size optimized results. Pixel clock driven from the bus clock.

    Technology
    /optimization
    Speed grade Area [gates]
    0.18u  typical 2050
    0.09u typical 2100

    DBLCD32  implementation results for ASIC devices.
    Speed optimized results. Pixel clock driven from the bus clock.