Digital Core Design

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DCAN FD

Configurable CAN Bus Controller with Flexible Data-Rate

    The DCAN FD is a standalone controller for the Controller Area Network (CAN), widely used in automotive and industrial applications. It conforms to Bosch CAN 2.0B specification (2.0B Active) and CAN FD (flexible data-rate).
    The improved protocol overcomes standard CAN limits: data can be transmitted faster than with 1 Mbit/s and the payload (data field) is up to 64 byte long and limited to 8 byte anymore. When only one node is transmitting, the bit-rate can be increased, because no nodes need to be synchronized. Of course, before the transmission of the ACK slot bit, the nodes need to be re-synchronized.
    The core has a simple CPU interface (8/16/32 bit configurable data width), with small or big endian addressing scheme. Hardware message filtering and 128 byte receive FIFO enable back-to-back message reception, with minimum CPU load. The DCAN FD is provided as HDL source code, allowing target use in FPGA or ASIC technologies.

    Watch the DCAN FD presentation on DCD's You Tube:

    Subskrybuj mój kanał w YouTube


    Performance

    Each core has been tested in variety of FPGA and ASIC technologies. Implementation results are summarized below.

    Implementation
    with CAN FD option
    Speed
    grade
    Logic Cells Memory
    bytes
    ARRIA V -6 1385 256
    CYCLONE V -8 1339 256
    STRATIX V -3 1383 256
           
    Implementation
    without CAN FD option
         
    ARRIA V -6 851 40
    CYCLONE V -8 831 40
    STRATIX V -3 867 40

    8-bit DCAN implementation results in ALTERA devices. 

    Implementation
    with CAN FD option
    Speed
    grade
    FF LUT Memory
    bytes
    KINTEX 7 -3 758 1655 256
    ARTIX 7 -3 760 1696 256
             
    Implementation
    without CAN FD option
           
    KINTEX 7 -3 476 1052 40
    ARTIX 7 -3 476 1047 40

    8-bit DCAN implementation results for XILINX devices. 

    Technology/optimization
    with CAN FD option
    Speed grade Area
    [gates]
    Fmax
    0.18u area typical 9 000 100 MHz
    0.18u speed typical 9 500 300 MHz
    0.09u area typical 8 400 200 MHz
    0.09u speed typical 9 900 400 MHz
           
    Technology/optimization
    without CAN FD option
         
    0.18u area typical 5800 100 MHz
    0.18u speed typical 6300 300 MHz
    0.09u area typical 5200 200 MHz
    0.09u speed typical 6700 400 MHz

    8-bit DCAN implementation results for ASIC devices.


    Key Features

    • Designed in accordance to ISO 11898-1:2015
    • Supports CAN 2.0B and CAN FD frames
    • Support up to 64 bytes data frames
    • Flexible data-rates supported
    • 8/16/32-bit CPU slave interface with small or big endianness
    • Simple interface allows easy connection to CPU
    • Supports both standard (11-bit identifier) and extended (29 bit identifier) frames
    • Data rate up to 8 Mbps
    • Hardware message filtering (dual/single filter)
    • 128 byte receive FIFO and transmit buffer
    • Overload frame is generated on FIFO overflow
    • Normal & Listen Only Mode
    • Transceiver Delay Compensation up to three data bit long
    • Single Shot transmission
    • Ability to abort transmission
    • Readable error counters
    • Last Error Code
    • Fully synthesizable
    • Static synchronous design with positive edge clocking and synchronous reset
    • No internal tri-states
    • Scan test ready
    • Available system interface wrappers:
      • AMBA - APB Bus
      • Altera Avalon Bus
      • Xilinx OPB Bus

    Applications

    • Automotive, industrial
    • Embedded communication systems

    Symbol

     qmr (31:0)
    dmr (31:0) 
    waddrmr (4:0) 
    raddrmr (4:0) 
    enrmr 
    enwmr 
     rxd
    txd 
     be (3:0)
     addr (5:0)
     datai (31:0)
     rd
     wr
     cs
     clk
     rst
    int 
    datao (31:0) 
     qmt (31:0)
    dmt (31:0) 
    waddrmt (4:0) 
    raddrmt (4:0) 
    enrmt 
    enwmt 

    Pins description

    PinTypeDescription
    qmr (31:0)inputRX DPRAM data output - configurable 8, 16, 32 bits wide
    rxdinputCAN receive data
    be (3:0)inputHost byte enable - set accprdig to Data bus size
    addr (5:0)inputHost Address bus
    datai (31:0)inputHost output Data bus - configurable 8, 16, 32 bits wide
    rdinputRead Data strobe
    wrinputWrite data strobe
    csinputChip select
    clkinputMain CPU clock
    rstinputReset
    qmt (31:0)inputTX DPRAM data output - configurable 8, 16, 32 bits wide
    dmr (31:0)outputRX DPRAM data input
    waddrmr (4:0)outputRX DPRAM write address
    raddrmr (4:0)outputRX DPRAM read address
    enrmroutputRX DPRAM read access
    enwmroutputRX DPRAM write enable
    txdoutputCAN Transmit data
    intoutputInterrupt request signal
    datao (31:0)outputHost input data bus - configurable 8, 16, 32 bits wide
    dmt (31:0)outputTX DPRAM data input - configurable 8, 16, 32 bits wide
    waddrmt (4:0)outputTXDPRAM write address
    raddrmt (4:0)outputTX DPRAM read address
    enrmtoutputTXDPRAM read enable
    enwmtoutputTX DPRAM write enable

    Block Diagram

    Receive FIFOReceive FIFO controller.
    RX RAM InterfaceInterface to external dual port memory used by the DCAN core, to store received frames.
    dmr (31:0)
    waddrmr (4:0)
    raddrmr (4:0)
    enrmr
    enwmr
    qmr (31:0)
    ACF Acceptance filterDecides whether incoming messages are accepted or not based upon filter registers settings.
    BRP Baud Rate PrescalerDefines the length of time quantum.
    BSP Bit Stream ProcessorTranslates messages into frames and vice versa.
    BTL Bit Timing LogicProcesses the bit time, calculates position of the sample point and performs synchronization.
    txd
    rxd
    EML Error Management LogicEML is responsible for fault confinement handling.
    IML Interface Management LogicInterprets commands from the CPU, provides interrupt and status indication.
    be (3:0)
    addr (5:0)
    datai (31:0)
    int
    datao (31:0)
    rd
    wr
    cs
    clk
    rst
    TX RAM InterfaceInterface to external dual port memory used by the DCAN core to store transmitted frames.
    dmt (31:0)
    waddrmt (4:0)
    raddrmt (4:0)
    enrmt
    enwmt
    qmt (31:0)
    Control bus DCAN internal control bus
    Data Bus DCAN Internal data bus

    Units

    Receive FIFO
    Receive FIFO controller.
    RX RAM Interface
    Interface to external dual port memory used by the DCAN core, to store received frames.
    ACF Acceptance filter
    Decides whether incoming messages are accepted or not based upon filter registers settings.

    BRP Baud Rate Prescaler
    Defines the length of time quantum.
    BSP Bit Stream Processor
    Translates messages into frames and vice versa.
    BTL Bit Timing Logic
    Processes the bit time, calculates position of the sample point and performs synchronization.

    EML Error Management Logic
    EML is responsible for fault confinement handling.
    IML Interface Management Logic
    Interprets commands from the CPU, provides interrupt and status indication.
    TX RAM Interface
    Interface to external dual port memory used by the DCAN core to store transmitted frames.