Digital Core Design

The Power of Intellectual Property

D16750

Configurable UART with FIFO and hardware flow control

    The D16750 is a soft Core of a Universal Asynchronous Receiver / Transmitter (UART), functionally identical to the TL16C750. The D16750 allows serial transmission in two modes - UART and FIFO. In the FIFO mode, internal FIFOs are activated allowing up to 512 bytes (plus 3 bits data error per byte in the RCVR FIFO) to be stored, both in receive and transmit directions. Our trustworthy core performs serial-to-parallel conversion on data characters, received from a peripheral device or from a MODEM, and a parallel-to-serial conversion on data characters, received from the CPU. The CPU can read acomplete status of the UART at any time, during the functional operation. The reported status information includes the type and condition of the transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt).
    The D16750 includes a programmable baud rate generator, which is capable of dividing the timing reference clock input by divisors of 1 to (216-1) and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic.
    What's more important, our revolutionary core has a complete MODEM control capability and a processor-interrupt system. Thanks to it, interrupts can be programmed in accordance to your requirements, minimizing the computing required to handle the communication link. The separate BAUD CLK line allows to set an exact transmission speed, while the UART internal logic is clocked with the CPU frequency. The configuration capability allows you to enable or disable during the Synthesis process the Modem Control Logic and FIFO's or change the FIFO's size. So, in applications with an area limitation and where the UART works only in the 16450 mode, disabling Modem Control and FIFO's, allow to save about 50% of logic resources.
    The core is perfect for applications, where the UART Core and a microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices.
    Thanks to a universal interface, the D16750 core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system.
    Moreover, we have implemented a selectable autoflow control feature in the FIFO mode. What does it mean for you? Thanks to this useful feature, you can significantly reduce software overload and increase system efficiency. It'll be done automatically by controlling serial data flow through the RTS output and the CTS input signals.

    The D16750 includes fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow. Our core is a technology independent design, that can be implemented in a variety of process technologies.


    Family summary

    UART Feature DμART D2692 D16450 D16550 D16750 D16552 D16752 D16950 D85C30
    FIFO Size - 2*8 - 2*16 2*64 4*16 x*2*64 2*128 4
    Multichannel option - - - - - + + - -
    Separate BAUD Clock line + - + + + + + + +
    Modem Control - - + + + + + + +
    False Start Bit detection + + + + + + + + +
    Status report + + + + + + + + +
    Internal diagnostic capabilities + + + + + + + + +
    Prioritized interrupt system - + + + + + + + +
    Break generation and detection - + + + + + + + +
    Fast mode CLK/4 - - - - o - o + -
    Half-Duplex RS485 - + - - o - o + +
    RS485 buffer enable - - - + + - + + +
    IRDA support - - - - o + - + -
    Additional CLK prescaler - - - - - - + - -
    1284 Parallel Port - - - - - + - - -
    Hardware flow control RTS/CTS - + - - + - + + +
    Software flow control Xon/Xoff - - - - - - + + -
    Isochronous mode - - - - - - - + +
    Detector of bad data in receiver FIFO - + - + + + + + +
    Special character detection - - - - - - + + -
    Software channel reset - - - - - - - + -
    4 byte device ID - - - - - - - + -
    Trigger levels for receiver and transmitter - - - - - - - + -
    Hardware flow control DTS/DTR - - - - - - - + -
    Optional FIFO size extension to 512 bytes - - - - + - + - -

    The main features of each UART family member have been summarized in table above. It gives a briefly member characterization helping you to select the most suitable IP Core for your application.

    Performance

    Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.

    Implementation Speed
    grade
    Area
    [TILES]
    Frequency
    [MHz]
    FUSION - 1177 82
    ProASIC3 - 1177 82
    ProASIC3E - 1177 79
    IGLOO - 1177 59
    IGLOO+ - 1185 55
    IGLOOe - 1217 62

    D16750 implementation results for ACTEL devices.  

    Implementation Speed
    grade
    LUTs/
    Slices
    Memory
    Blocks
    Frequency
    [MHz]
    Zynq-7000 -3 271 1 330
    Zynq -3 353/183 2 230
    Kintex Ultra Scale -3 273 1 350
    Kintex 7 -3 356/171 2 403
    Artix 7 -3 334/180 2 203
    Virtex Ultra Scale -3 273 1 350
    Virtex 7 -3 357/170 2 372
    Virtex 6 -2 312/132 2 272
    Virtex 5 -2 352/124 2 276
    Virtex 4 -12 443/314 2 229
    Spartan 6 -3 352/123 2 168
    Spartan 3E -5 442/320 2 130
    Spartan 3 -5 442/319 2 116

    D16750 implementation results for XILINX devices.  


    Implementation Speed
    grade
    Area
    [LC]
    Memory
    Bits
    Frequency
    [MHz]
    ARIA GX -6 381/243 1 216 228
    ARIA V -6 365/283 1 216 214
    CYCLONE -6 488 1 216 170
    CYCLONE II -6 496 1 216 197
    CYCLONE III -6 498 1 216 247
    CYCLONE IV -6 495 1 216 250
    CYCLONE V -6 365/243 1 216 188
    STRATIX -5 488 1 216 180
    STRATIX II -3 382/245 1 216 333
    STRATIX III -2 382/297 1 216 454
    STRATIX IV -2 369/263 1 216 457
    STRATIX GX -5 488 1 216 185
    STRATIX 2 GX -3 380/244 1 216 317

    D16750 implementation results for ALTERA devices.  

    Implementation Speed
    grade
    Area
    [LUT/PFU]
    Frequency
    [MHz]
    EC - 792/253 134
    ECP - 792/253 127
    XP - 792/253 107
    ECP2 - 693/245 172
    ECP2M - 480/240 172
    SC - 726/245 214
    XP2 - 480/240 126

    D16750 implementation results for LATTICE devices. 


    Key Features

    • Software compatible with 16450, 16550 and 16750 UARTs
    • Configuration capability
    • Separate configurable BAUD clock line
    • Majority Voting Logic
    • Supports RS232 and RS485 standards
    • Two modes of operation: UART mode and FIFO mode
      • In the FIFO mode transmitter and receiver are each buffered with 64 byte FIFO to reduce the number of interrupts presented to the CPU
      • In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
    • Configurable FIFO size allowing up to 512 levels deep FIFOs in both Rx and Tx directions.
    • Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
    • Independently controlled transmit, receive, line status and data set interrupts
    • False start bit detection
    • 16 bit programmable baud generator
    • Independent receiver clock input
    • MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)
    • Programmable automatic Hardware Flow Control logic through Auto-RTS and Auto-CTS
    • Fully programmable serial-interface characteristics:
      • 5-, 6-, 7-, or 8-bit characters
      • Even, odd, or no-parity bit generation and detection
      • 1-, 1.5-, or 2-stop bit generation
      • Internal baud generator
    • Complete status reporting capabilities
    • Line break generation and detection. Internal diagnostic capabilities:
      • Loop-back controls for communications link fault isolation
      • Break, parity, overrun, framing error simulation
    • Full prioritized interrupt system controls
    • Available system interface wrappers:
      • AMBA - APB Bus
      • Altera Avalon Bus
      • Xilinx OPB Bus
    • Fully synthesizable

    Applications

    • Serial Data communications applications
    • Modem interface
    • Embedded microprocessor boards

    Configuration

    The following parameters of the D16750 core can be easy adjusted to requirements of proprietary application and technology. Core configuration can be effortlessly done by changing appropriate constants in package file. There is no need to change any part of the code.

    • Baud generator: enable / disable
    • External RCLK source: enable / disable
    • External BAUDCLK source: enable / disable
    • Modem Control: enable / disable
    • SCR register: enable / disable
    • FIFO Control logic: enable / disable
    • FIFO Size: normal 16/64 / large, up to 512

    Symbol

     clk
     rst
     rclk
     si
    so 
    temt 
     cts
     dsr
     dcd
     ri
    rts 
    dtr 
    out1 
    out2 
    intr 
     datai (7:0)
     rd
     wr
     cs
     addr (2:0)
    datao (7:0) 
    ddis 
    txrdy 
    rxrdy 
     baudclken
     baudclk
    baudout 

    Pins description

    PinTypeDescription
    clkinputGlobal clock
    rstinputGlobal reset
    rclkinputReceiver clock
    siinputSerial data input
    ctsinputClear to send input
    dsrinputData set ready input
    dcdinputData carrier detect input
    riinputRing indicator input
    datai (7:0)inputParallel data input
    rdinputRead input
    wrinputWrite input
    csinputChip select
    addr (2:0)inputAddress bus
    baudclkeninputBaud generator clock enable
    baudclkinputBaud generator clock
    sooutputSerial data output
    temtoutputTransmitter Empty - used to control RS485 buffer
    rtsoutputRequest to send output
    dtroutputData terminal ready output
    out1outputOutput 1
    out2outputOutput 2
    introutputInterrupt request output
    datao (7:0)outputParallel data output
    ddisoutputDriver disable output
    txrdyoutputTransmitter ready output
    rxrdyoutputReceiver ready output
    baudoutoutputBaud generator output

    Block Diagram

    Receiver FIFOThe Rx FIFO is 16 levels (16550), 64 levels (16750) or 128 levels (16950) deep. It receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time, if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it will be completely full. It will not accept any more data when it is full. These data entering the Rx shift register will set the Overrun Error flag.
    Receiver ControlThe D16X50 receiver has its own independent clock input RCLK. Receiving starts when the falling edge on Serial Input (SI) during IDLE State is being detected. After starting, the SI input is sampled every 16 RCLK cycles, as it is shown in figure below. When the logic 1 state is detected during START bit, it means that the False Start bit was detected and receiver back to the IDLE state.
    rclk
    si
    Transmitter FIFOThe Tx portion of the UART transmits data through SO, as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO, if it is currently full. Loading to the Tx FIFO will be enabled again, as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt.
    Transmitter ControlTransmitter Control module controls transmission of written to THR (Transmitter Holding Register) character via serial output SO. New transmission starts on the next overflow signal of internal baud generator (the worst case delay: 1 baudout cycle), after writing to THR register or Transmitter FIFO. Transmission control contains THR register and transmitter shift register.
    so
    temt
    Modem Control LogicModem Control Logic monitors the interface with the MODEM, data set or a peripheral device emulating MODEM.
    rts
    cts
    dtr
    dsr
    dcd
    ri
    out1
    out2
    Interrupt ControllerD16X50 UARTs got fully prioritized interrupt system controller. It controls interrupt requests to the CPU and interrupt priority. Interrupt controller contains Interrupt Enable (IER) and Interrupt Identification (IIR) registers.
    intr
    Data Bus BufferData Bus Buffer accepts inputs from the system bus and generates control signals for the other UART functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WR signals are active low and qualified by CS; RD and WR are ignored unless the UART has been selected by holding CS low.
    datai (7:0)
    datao (7:0)
    rd
    wr
    cs
    ddis
    txrdy
    rxrdy
    addr (2:0)
    Baud GeneratorThe UART contains a programmable 16 bit baud generator, that divides clock input by a divisor, in the range between 1 and (216-1). The output frequency of the baud generator is 16× the baud rate. The formula for the divisor is:

    divisor=frequency/(16*baudrate)

    Two 8-bit registers, called divisor latches DLL and DLM, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded on the CLK rising edge following the write to DLL or DLM, to prevent long counts on initial load.
    baudout
    baudclken
    baudclk
    clk
    rst
    D16550 D16XXX UART internal data bus

    Units

    Receiver FIFO
    The Rx FIFO is 16 levels (16550), 64 levels (16750) or 128 levels (16950) deep. It receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time, if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it will be completely full. It will not accept any more data when it is full. These data entering the Rx shift register will set the Overrun Error flag.
    Receiver Control
    The D16X50 receiver has its own independent clock input RCLK. Receiving starts when the falling edge on Serial Input (SI) during IDLE State is being detected. After starting, the SI input is sampled every 16 RCLK cycles, as it is shown in figure below. When the logic 1 state is detected during START bit, it means that the False Start bit was detected and receiver back to the IDLE state.
    Transmitter FIFO
    The Tx portion of the UART transmits data through SO, as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO, if it is currently full. Loading to the Tx FIFO will be enabled again, as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt.

    Transmitter Control
    Transmitter Control module controls transmission of written to THR (Transmitter Holding Register) character via serial output SO. New transmission starts on the next overflow signal of internal baud generator (the worst case delay: 1 baudout cycle), after writing to THR register or Transmitter FIFO. Transmission control contains THR register and transmitter shift register.
    Modem Control Logic
    Modem Control Logic monitors the interface with the MODEM, data set or a peripheral device emulating MODEM.
    Interrupt Controller
    D16X50 UARTs got fully prioritized interrupt system controller. It controls interrupt requests to the CPU and interrupt priority. Interrupt controller contains Interrupt Enable (IER) and Interrupt Identification (IIR) registers.

    Data Bus Buffer
    Data Bus Buffer accepts inputs from the system bus and generates control signals for the other UART functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WR signals are active low and qualified by CS; RD and WR are ignored unless the UART has been selected by holding CS low.
    Baud Generator
    The UART contains a programmable 16 bit baud generator, that divides clock input by a divisor, in the range between 1 and (216-1). The output frequency of the baud generator is 16× the baud rate. The formula for the divisor is:

    divisor=frequency/(16*baudrate)

    Two 8-bit registers, called divisor latches DLL and DLM, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded on the CLK rising edge following the write to DLL or DLM, to prevent long counts on initial load.