Digital Core Design

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DUSB2-ULPI

USB 2.0 Device Controller with ULPI interface

The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver. The DUSB2-ULPI contains a USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic. The DUSB2-ULPI is designed to support 12 Mb/s "Full Speed" (FS) and 480 Mb/s "High Speed" (HS) serial data transmission rates. The design is technology independent and thus can be implemented in a variety of process technologies. This core strictly conforms to the USB Specification v 2.0 and ULPI v2.0. It is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow.


Key Features

  • Full compliance with the USB 2.0 specification
  • Full-speed 12 Mbps operation
  • High-speed 480 Mbps operation
  • Software configurable EP0 control endpoint size 8-64 bytes
  • Software configurable 15 IN/OUT endpoints:
    • configurable number of endpoints
    • configurable type of each endpoint: INTERRUPT, BULK or ISOCHRONOUS
    • configurable direction of each endpoint
    • configurable size of each endpoint: 8-1024 bytes
  • Supports ULPI Transceiver Macrocell Interface
  • Synchronous RAM interface for FIFOs
  • Suspend and resume power management functions
  • Simple interface allows easy connection to the 8-, 16-, 32-bit CPUs
  • Allows operation from a wide range of CPU clock frequencies
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking
  • No internal tri-states
  • Scan test ready

Applications

  • Human Interface Devices like keyboards, mouse or game peripherals
  • Mass Storage devices like flash disk, mp3 or mp4 player
  • GPS navigation system
  • Digital Camera
  • Cellular phone
  • Audio devices like microphone or speakers
  • Printer
  • Scanner

Symbol

 ulpiclk
 datai (7:0)
 dir
 nxt
datao (7:0) 
stp 
 cpuclk
 cpuaddress (8:0)
 cpudatai(CS-1:0)
 cpuwr
 cpurd
 cpube(3:0)
cpudatao(CS-1:0) 
irq 
 sramdataia(FS-1:0)
 sramdataib(FS-1:0)
sramaddra (14:0) 
sramaddrb (14:0) 
sramdataoa(FS-1:0) 
sramdataob(FS-1:0) 
sramwea 
sramweb 
 dmaaddress (3:0)
 dmadatai(DS-1:0)
 dmab (3:0)
 dmard
 dmawr
dmadatao(DS-1:0) 

Pins description

PinTypeDescription
ulpiclkinputULPI clock @60 MHz
datai (7:0)inputULPI parallel data input bus
dirinputULPI direction
nxtinputULPI next data
cpuclkinputCPU clock
cpuaddress (8:0)inputCPU address bus
cpudatai(CS-1:0)inputCPU data input bus
cpuwrinputCPU write
cpurdinputCPU read
cpube(3:0)inputCPU byte enable
sramdataia(FS-1:0)inputSRAM port A data input bus
sramdataib(FS-1:0)inputSRAM port B data input bus
dmaaddress (3:0)inputDMA address input bus
dmadatai(DS-1:0)inputDMA data input bus
dmab (3:0)inputDMA byte enable
dmardinputDMA read
dmawrinputDMA write
datao (7:0)outputULPI parallel data output bus
stpoutputULPI stop data
cpudatao(CS-1:0)outputCPU data output bus
irqoutputCPU interrupt request
sramaddra (14:0)outputSRAM port A address bus
sramaddrb (14:0)outputSRAM port B address bus
sramdataoa(FS-1:0)outputSRAM port A data output bus
sramdataob(FS-1:0)outputSRAM port B data output bus
sramweaoutputSRAM port A write enable
sramweboutputSRAM port B write enable
dmadatao(DS-1:0)outputDMA data output bus

Block Diagram

EP0Special bidirectional endpoint used for device configuration. Allows generic USB control and status access.
EP10Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP1Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP11Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP12Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP13Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP13Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP14Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP14Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP15Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP2Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP3Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP3Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP4Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP5Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP6Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP7Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP8Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP9Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
ULPI interfaceThe ULPI interface is clocked by ULPICLK clock @60MHz and manages communication with USB 2.0 Transceiver Macrocell. It is responsible for reset detection, speed handshake, token, data and handshake packet reception and transmission.
ulpiclk
datai (7:0)
dir
nxt
datao (7:0)
stp
CPU interfaceThe CPU interface module is clocked by CPUCLK clock and manages communication with some CPU. In this module DUSB2-ULPI core configuration and status registers are being located. CPU bus size is configurable as 8, 16 or 32-bit wide.
cpuclk
cpuaddress (8:0)
cpudatai(CS-1:0)
cpuwr
cpurd
cpube(3:0)
cpudatao(CS-1:0)
irq
SRAM interfaceThe SRAM interface module manages communication with Synchronous Random Access Memory. It generates address, read and write signals for the SRAM memory and buffers data bytes during the FIFO read and write operations.
sramdataia(FS-1:0)
sramdataib(FS-1:0)
sramaddra (14:0)
sramaddrb (14:0)
sramdataoa(FS-1:0)
sramdataob(FS-1:0)
sramwea
sramweb
DMA interface
dmaaddress (3:0)
dmadatai(DS-1:0)
dmab (3:0)
dmard
dmawr
dmadatao(DS-1:0)

Units

EP0
Special bidirectional endpoint used for device configuration. Allows generic USB control and status access.
EP10
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP1
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP11
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP12
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP13
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP13
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP14
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP14
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP15
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP2
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP3
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP3
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP4
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP5
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP6
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP7
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP8
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP9
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
ULPI interface
The ULPI interface is clocked by ULPICLK clock @60MHz and manages communication with USB 2.0 Transceiver Macrocell. It is responsible for reset detection, speed handshake, token, data and handshake packet reception and transmission.
CPU interface
The CPU interface module is clocked by CPUCLK clock and manages communication with some CPU. In this module DUSB2-ULPI core configuration and status registers are being located. CPU bus size is configurable as 8, 16 or 32-bit wide.

SRAM interface
The SRAM interface module manages communication with Synchronous Random Access Memory. It generates address, read and write signals for the SRAM memory and buffers data bytes during the FIFO read and write operations.
DMA interface