Digital Core Design

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DUSB2-ULPI

USB 2.0 Device Controller with ULPI interface

The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver. The DUSB2-ULPI contains a USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic. The DUSB2-ULPI is designed to support 12 Mb/s "Full Speed" (FS) and 480 Mb/s "High Speed" (HS) serial data transmission rates. The design is technology independent and thus can be implemented in a variety of process technologies. This core strictly conforms to the USB Specification v 2.0 and ULPI v2.0. It is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow.


Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

LATTICE

Device Speed grade cpuclk Fmax ulpiclk Fmax
SC -7 270 MHz >100 MHz
ECP2 -7 190 MHz >100 MHz
ECP2M -7 170 MHz >100 MHz
XP2 -7 160 MHz >100 MHz

Core's performance in LATTICE devices

 

Component Area [LUT4s] Area [FFs]
CPU interface 215 170
ULPI interface 340 280
SRAM interface 110 95
EP0 endpoint 145 140
EP1 endpoint 155 155
EP2 endpoint 155 155
Total area 1120 995

Core's components area utilization in ECP2 and ECP2M families

 

Component Area [LUT4s] Area [FFs]
CPU interface 240 170
ULPI interface 380 280
SRAM interface 120 95
EP0 endpoint 160 140
EP1 endpoint 175 155
EP2 endpoint 175 155
Total area 1250 995

Core's components area utilization in XP2 family

 

Component Area [LUT4s] Area [FFs]
CPU interface 200 170
ULPI interface 320 280
SRAM interface 100 95
EP0 endpoint 130 140
EP1 endpoint 140 155
EP2 endpoint 140 155
Total area 1030 995

Core's components area utilization in SC family

 

XILINX

Family Device Speed
grade
LUT Slice cpu Fmax
SPARTAN-3 xc3s200 -5 1761 1360 121 MHz
SPARTAN-3E xc3s250e -5 1784 1357 135 MHz
SPARTAN-6 xc6slx4 -3 1510 588 212 MHz
VIRTEX-4 xc4vfx12 -12 1780 1358 256 MHz
VIRTEX-5 xc5vlx20t -2 1453 840 300 MHz
VIRTEX-6 xc6vlx75t -3 1452 692 312 MHz
VIRTEX-7 xc7vx330t -3 1510 742 384 MHz
KINTEX-7 xc7k70t -3 1510 714 384 MHz
ARTIX-7 xc7a100t -3 1400 700 263 MHz
VIRTEX UltraScale xcvu065 -3 1253 272 500 MHz
ZYNQ-7000 xc7z010 -3 1252 492 330 MHz

Core's performance in XILINX devices

 

Component Area [Slices] Area [FFs]
CPU interface 225 170
ULPI interface 315 280
SRAM interface 115 95
EP0 endpoint 150 140
EP1 endpoint 160 155
EP2 endpoint 160 155
Total area 1125 995

Core's components area utilization in XILINX devices except the VIRTEX-5 family

 

Component Area [Slices] Area [FFs]
CPU interface 120 170
ULPI interface 165 280
SRAM interface 65 95
EP0 endpoint 80 140
EP1 endpoint 85 155
EP2 endpoint 85 155
Total area 600 995

Core's components area utilization in XILINX VIRTEX-5 devices


ALTERA

Device Speed
grade
cpuclk Fmax ulpiclk Fmax
CYCLONE-II -6 150 MHz >100 MHz
CYCLONE-III -6 180 MHz >100 MHz
STRATIX-II -3 250 MHz >100 MHz
STRATIX-III -2 270 MHz >100 MHz
Arria GX -6 200 MHz >100 MHz

Core's implementation in ALTERA devices.

 

Component Area [LC] Area [FFs]
CPU interface 270 170
ULPI interface 400 280
SRAM interface 130 95
EP0 endpoint 180 140
EP1 endpoint 190 155
EP2 endpoint 190 155
Total area 1360 995

Core's components area utilization in STRATIX-II, STRATIX-III and Arria GX families

 

Component Area [LC] Area [FFs]
CPU interface 390 170
ULPI interface 540 280
SRAM interface 190 95
EP0 endpoint 260 140
EP1 endpoint 300 155
EP2 endpoint 300 155
Total area 1980 995

Core's components area utilization in CYCLONE-II and CYCLONE-III families

ASIC

Device Optimization cpuclk Fmax ulpiclk Fmax
0.25u typical area >200 MHz >100 MHz
0.25u typical speed >200 MHz >100 MHz
0.18u typical area >200 MHz >100 MHz
0.18u typical speed >200 MHz >100 MHz
0.13u typical area >200 MHz >100 MHz
0.13u typical speed >200 MHz >100 MHz

Core's performance in ASIC devices

 

Component Area [Gates]
DUSB2-ULPI+EP0 5700
EP1 endpoint 2100
EP2 endpoint 2100
Total area 9900

Core's components area utilization

 


Key Features

  • Full compliance with the USB 2.0 specification
  • Full-speed 12 Mbps operation
  • High-speed 480 Mbps operation
  • Software configurable EP0 control endpoint size 8-64 bytes
  • Software configurable 15 IN/OUT endpoints:
    • configurable number of endpoints
    • configurable type of each endpoint: INTERRUPT, BULK or ISOCHRONOUS
    • configurable direction of each endpoint
    • configurable size of each endpoint: 8-1024 bytes
  • Supports ULPI Transceiver Macrocell Interface
  • Synchronous RAM interface for FIFOs
  • Suspend and resume power management functions
  • Simple interface allows easy connection to the 8-, 16-, 32-bit CPUs
  • Allows operation from a wide range of CPU clock frequencies
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking
  • No internal tri-states
  • Scan test ready

Applications

  • Human Interface Devices like keyboards, mouse or game peripherals
  • Mass Storage devices like flash disk, mp3 or mp4 player
  • GPS navigation system
  • Digital Camera
  • Cellular phone
  • Audio devices like microphone or speakers
  • Printer
  • Scanner

Symbol

 ulpiclk
 datai (7:0)
 dir
 nxt
datao (7:0) 
stp 
 cpuclk
 cpuaddress (8:0)
 cpudatai(CS-1:0)
 cpuwr
 cpurd
 cpube(3:0)
cpudatao(CS-1:0) 
irq 
 sramdataia(FS-1:0)
 sramdataib(FS-1:0)
sramaddra (14:0) 
sramaddrb (14:0) 
sramdataoa(FS-1:0) 
sramdataob(FS-1:0) 
sramwea 
sramweb 
 dmaaddress (3:0)
 dmadatai(DS-1:0)
 dmab (3:0)
 dmard
 dmawr
dmadatao(DS-1:0) 

Pins description

PinTypeDescription
ulpiclkinputULPI clock @60 MHz
datai (7:0)inputULPI parallel data input bus
dirinputULPI direction
nxtinputULPI next data
cpuclkinputCPU clock
cpuaddress (8:0)inputCPU address bus
cpudatai(CS-1:0)inputCPU data input bus
cpuwrinputCPU write
cpurdinputCPU read
cpube(3:0)inputCPU byte enable
sramdataia(FS-1:0)inputSRAM port A data input bus
sramdataib(FS-1:0)inputSRAM port B data input bus
dmaaddress (3:0)inputDMA address input bus
dmadatai(DS-1:0)inputDMA data input bus
dmab (3:0)inputDMA byte enable
dmardinputDMA read
dmawrinputDMA write
datao (7:0)outputULPI parallel data output bus
stpoutputULPI stop data
cpudatao(CS-1:0)outputCPU data output bus
irqoutputCPU interrupt request
sramaddra (14:0)outputSRAM port A address bus
sramaddrb (14:0)outputSRAM port B address bus
sramdataoa(FS-1:0)outputSRAM port A data output bus
sramdataob(FS-1:0)outputSRAM port B data output bus
sramweaoutputSRAM port A write enable
sramweboutputSRAM port B write enable
dmadatao(DS-1:0)outputDMA data output bus

Block Diagram

EP0Special bidirectional endpoint used for device configuration. Allows generic USB control and status access.
EP10Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP1Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP11Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP12Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP13Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP13Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP14Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP14Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP15Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP2Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP3Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP3Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP4Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP5Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP6Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP7Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP8Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP9Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
ULPI interface
ulpiclk
datai (7:0)
dir
nxt
datao (7:0)
stp
CPU interface
cpuclk
cpuaddress (8:0)
cpudatai(CS-1:0)
cpuwr
cpurd
cpube(3:0)
cpudatao(CS-1:0)
irq
SRAM interface
sramdataia(FS-1:0)
sramdataib(FS-1:0)
sramaddra (14:0)
sramaddrb (14:0)
sramdataoa(FS-1:0)
sramdataob(FS-1:0)
sramwea
sramweb
DMA interface
dmaaddress (3:0)
dmadatai(DS-1:0)
dmab (3:0)
dmard
dmawr
dmadatao(DS-1:0)

Units

EP0
Special bidirectional endpoint used for device configuration. Allows generic USB control and status access.
EP10
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP1
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP11
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP12
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP13
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP13
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP14
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP14
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP15
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP2
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP3
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP3
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP4
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP5
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP6
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP7
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP8
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP9
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
ULPI interface
CPU interface

SRAM interface
DMA interface