Serial Peripheral Interface – Slave
The DSPIS is a fully configurable SPI slave device, designated to operate with passive devices, like memories, LCD drivers etc. It allows you to configure polarity and phase of serial clock signal SCK. A serial clock line (SCK) synchronizes information shifting and sampling on the two independent serial data lines. Moreover, the data is simultaneously transmitted and received.
The DSPIS system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The clock control logic (CLK/4) allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. The DSPIS allows the SPI Master to communicate with passive devices. When transmission starts (SS Line goes low), the first portion of data is copied to the address register and then to the ADDRESS bus output, after transmission of the address, the DSPIS generates the read signal (RD) and copy DATAI bus contents to the transmitter shift register and prepare data to be exchanged with the SPI Master. During the next portion of data transmission, the DSPIS simultaneously transfers the data out and in. When the first portion of data is received, the DSPIS asserts DATAO bus generates the write signal (WE), then increments ADDRESS bus performs a read operation and prepare another data portion to be exchanged with SPI master. Transmission is ended when the SS line goes high. The DSPIS is a technology independent design, that can be implemented in a variety of process technologies. It's also fully customizable, which means, that the configuration is tailored to your requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow.
Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.
DSPIS implementation results for ACTEL devices.
|EC||-5||94 / 55||222|
|ECP||-5||94 / 55||226|
|XP||-5||94 / 55||219|
|ECP2||-7||90 / 55||324|
|ECP2M||-7||69 / 49||345|
|SC||-7||84 / 55||489|
|XP2||-7||69 / 49||306|
DSPIS implementation results for LATTICE devices. All features have been included.
DSPIS implementation results for XILINX devices.
[LE] [ALUT / REG]
|STRATIX-IV||-||64 / 65||>600|
DSPIS implementation results for ALTERA devices. All features have been included.
- Full duplex synchronous serial data transfer
- Slave operation
- Automatic read and write operations
- Automatic address incrementation after any data portion transfer
- Configurable address and data length
- Configurable SCK phase and polarity
- Supports speeds up 1/4 of system clock
- Simple interface allows easy connection to passive devices and SPI Master
- Four transfer formats supported
- Simple interface allows easy connection to microcontrollers
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Embedded microprocessor boards
- Consumer and professional audio/video
- Home and automotive radio
- Low-power applications
- Communication systems
- Digital multimeters
|ss||input||SPI Slave Select input.|
|datai (7:0)||input||Passive device data bus|
|si||input||Slave serial data input|
|cpha||input||CPHA - SCK clock phase, defines phase of the SCK clock input.|
|cpol||input||CPOL- SCK Clock polarity.|
|SCK||input||SPI Serial Clock input|
|datao (7:0)||output||Passive device data bus|
|address (7:0)||output||Passive device address bus|
|rd||output||Passive device read strobe|
|we||output||Passive device write strobe|
|so||output||Slave serial data output|
|SPI ControllerDetects begin and the end of SPI transfer. Manages data exchange between DSPIS and passive device controlled by DSPIS, and increment Address Register (SPAD) after any successful transfer.|
|Address registerHolds address presented on Address bus. Its contents is incremented every single data portion sent/received serially through the SPI bus.|
|Data registerHolds data read from passive device, to be sent serially to the SPI Master.|
|Shift registerIt is the central element in the SPI system. When SPI transfer occurs, an 8-bit character is shifted out on data pin while a different 8-bit character is simultaneously moved in a second data pin. Another way to view this transfer is when an 8-bit shift register in the master and another 8-bit shift register in the slave are connected as a circular 16-bit shift register. When a transfer occurs, this distributed shift register is moved 8-bit positions. Moreover, the characters in the master and slave are effectively exchanged.|
|SPI Clock LogicControls phase and polarity of the SCK clock line. In the same time it detects correct sample and shift edge for the Shift register. SPI Clock Logic allows user to select any of four combinations of serial clock (SCK) phase and polarity using two pins CPHA and CPOL. The clock polarity is specified by the CPOL, which selects an active high or active low clock and has no significant effect on the transfer format. The clock phase CPHA selects one of two fundamentally different transfer formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers to allow a master device to communicate with peripheral slaves having different requirements. The flexibility of the SPI system on the DSPIS allows direct interface to almost any existing synchronous serial peripheral.|
|SPI bus SPI virtual bus|