Digital Core Design

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DMAC

10/100 Mb Media Access Controller

    Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external PHY device enables network functionality in design. It is capable to transmit and receive Ethernet frames to and from the network. Half and full duplex modes are supported, as well 10 and 100 Mbit/s speed. The Core is able to work with wide range of processors: 8, 16 and 32 bit data bus, either little or big endian byte order format. The DMAC provides static configuration of PHY IC. Please remember that our design is technology independent and thus can be implemented in variety of process technologies. This Core strictly conforms to IEEE 802.3 standard.


    Performance

    Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.

    Implementation Speed
    grade
    Utilized Area
    [Slices/LUTs]
    Frequency
    [MHz]
    clk / rxclk / txclk
    VIRTEX-6 -2 341/883+4kB RAM 275 / 230 / 230
    VIRTEX-5 -2 399/979+4kB RAM 225 / 220 / 200
    VIRTEX-4 -12 877/1333+4kB RAM 170 / 150 / 170
    VIRTEX-II -6 870/1315+4kB RAM 140 / 115 / 110
    SPARTAN-6 -3 344/845+4kB RAM 130 / 130 / 130
    SPARTAN-3E -5 870/1316+4kB RAM 120 / 100 / 100
    SPARTAN-3 -5 878/1323+4kB RAM 120 / 90 / 90

    DMAC implementation results for XILINX devices.
    All features have been included. 

    Implementation Speed
    grade
    Utilized Area
    [LC]
    Frequency
    [MHz]
    clk / rxclk / txclk
    STRATIX IV -1 876+4kB RAM 420 / 380 / 350
    STRATIX III -2 878+4kB RAM 370 / 400 / 350
    STRATIX II -3 879+4kB RAM 270 / 280 / 270
    CYCLONE IV -6 1304+4kB RAM 200 / 220 / 200
    CYCLONE III -6 1302+4kB RAM 190 / 190 / 200
    CYCLONE II -6 1292+4kB RAM 158 / 170 / 180
    STRATIX GX -5 1255+4kB RAM 152 / 156 / 138
    STRATIX -5 1255+4kB RAM 162 / 147 / 137
    CYCLONE -6 1254+4kB RAM 148 / 133 / 133

    DMAC implementation results for ALTERA devices.
    All features have been included. 

    Implementation Speed
    grade
    Minimum Area
    [gates]
    Top Frequency
    Fmax [MHz]
    clk / txclk / rxclk
    0.25 um typical 7800 gates 250 / >50 / >50
    0.18 um typical 7800 gates 360 / >50 / >50
    0.09 um typical 6400 gates 800 / >50 / >50
    0.06 um typical 6300 gates 900 / >50 / >50
    0.04 um typical 6300 gates 1000/ >50/ >50

    DMAC implementation results for ASIC devices.
    All features have been included. 


    Key Features

    • Conforms to IEEE 802.3-2002 specification
    • Configurable width CPU interface with little or big endianess:
      • 8-bit
      • 16-bit
      • 32-bit
    • Simple interface allows easy connection to CPU
    • Narrow address bus (4 bits) with indirect I/O interface for transmitted and received data dual port memories
    • Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs
    • Media Independent Interface (MII) for connection to external 10/100 Mbps PHY transceivers
    • Supports full and half duplex operation at 10 Mbps or 100 Mbps
    • CRC-32 algorithm:
      • calculates the FCS nibble at a time
      • automatic FCS generation and checking
      • able to capture frames with CRC errors if required
    • Dynamic PHY configuration by STA management interface
    • Early receive and transmit interrupts to increase data throughput
    • Programmable MAC address
    • Promiscuous mode support
    • Allows operation from a wide range of input bus clock frequencies
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking
    • No internal tri-states
    • Lite design, small gate count and fast operation
    • Scan test ready

    Applications

    • Embedded microprocessor boards
    • Networking devices (Network Interface Cards, routers, switches)
    • Communication systems

    Symbol

     qmr (31:0)
    dmr (31:0) 
    waddrmr (8:0) 
    raddrmr (8:0) 
    enrmr 
    enwmr 
     rxclk
     rxdv
     rxer
     rxdata (3:0)
     mdi
    mdo 
    mdc 
    mdoe 
     datai1 (31:0)
     be1 (3:0)
     rd
     wr
     addr (3:0)
     clk
     rst
    datao1 (31:0) 
    irq 
     qmt (31:0)
    waddrmrt (8:0) 
    raddrmt (8:0) 
    enwmt 
    enrmt 
    dmt (31:0) 
     txclk
     crs
     col
    txer 
    txen 
    txdata (3:0) 

    Pins description

    PinTypeDescription
    qmr (31:0)inputRX DPRAM data output
    rxclkinputEthernet receive clock
    rxdvinputEthernet receive data valid
    rxerinputEthernet receive error
    rxdata (3:0)inputEthernet receive data
    mdiinputManagement data input
    datai1 (31:0)inputHost output data bus
    be1 (3:0)inputHost byte enable
    rdinputRead data strobe
    wrinputWrite data strobe
    addr (3:0)inputHost address bus
    clkinputGlobal clock
    rstinputGlobal reset
    qmt (31:0)inputTX DPRAM data output
    txclkinputEthernet transmit clock
    crsinputEthernet carrier sense
    colinputEthernet collision detection
    dmr (31:0)outputRX DPRAM data input
    waddrmr (8:0)outputRX DPRAM write address
    raddrmr (8:0)outputRX DPRAM read address
    enrmroutputRX DPRAM read enable
    enwmroutputRX DPRAM write enable
    mdooutputManagement data output
    mdcoutputManagement clock
    mdoeoutputManagement data output enable
    datao1 (31:0)outputHost input data bus
    irqoutputInterrupt signal
    waddrmrt (8:0)outputTX DPRAM write address
    raddrmt (8:0)outputTX DPRAM read address
    enwmtoutputTX DPRAM write enable
    enrmtoutputTX DPRAM read enable
    dmt (31:0)outputTX DPRAM data input
    txeroutputEthernet transmit error
    txenoutputEthernet transmit enable
    txdata (3:0)outputEthernet transmit data

    Block Diagram

    RX RAM InterfaceInterfaces to external dual port memories, used by the DMAC core to store received frames.
    qmr (31:0)
    dmr (31:0)
    waddrmr (8:0)
    raddrmr (8:0)
    enrmr
    enwmr
    Receive moduleThis module is responsible for receiving frames from the Ethernet. Provides necessary functions for frame decapsulation, CRC checking, address recognizing and error detection.
    rxclk
    rxdv
    rxer
    rxdata (3:0)
    STA interfaceStation Management entity provides capability to communicate with PHY by simple serial management interface and dynamically setup transmission parameters. PHY can be configured by DMAC at any time, allowing easy management of PHY behavior.
    mdo
    mdc
    mdoe
    mdi
    Control and I/O logicThis module provides interface to CPU/BUS. It exchanges data and control logic with transmit and receive modules, thus controls these to perform transmit and receive operations. Proper data alignment and bytes order is performed inside this unit.
    1 - data bus can be configured as 8-, 16- or 32- bit depends on processor's bus size
    datai1 (31:0)
    datao1 (31:0)
    irq
    be1 (3:0)
    rd
    wr
    addr (3:0)
    clk
    rst
    TX RAM InterfaceInterfaces to external dual port memories, used by the DMAC core to store transmitted frames.
    waddrmrt (8:0)
    raddrmt (8:0)
    qmt (31:0)
    enwmt
    enrmt
    dmt (31:0)
    Synchronization logicThere are 3 clock domains in the DMAC core. This module performs synchronization between these domains and assures correct data exchange between these domains.
    Transmit modulePerforms transmit management functions, sends frames to Ethernet medium. It is responsible for proper frame creation and response to PHY signals.
    txer
    txen
    txdata (3:0)
    txclk
    crs
    col

    Units

    RX RAM Interface
    Interfaces to external dual port memories, used by the DMAC core to store received frames.
    Receive module
    This module is responsible for receiving frames from the Ethernet. Provides necessary functions for frame decapsulation, CRC checking, address recognizing and error detection.
    STA interface
    Station Management entity provides capability to communicate with PHY by simple serial management interface and dynamically setup transmission parameters. PHY can be configured by DMAC at any time, allowing easy management of PHY behavior.

    Control and I/O logic
    This module provides interface to CPU/BUS. It exchanges data and control logic with transmit and receive modules, thus controls these to perform transmit and receive operations. Proper data alignment and bytes order is performed inside this unit.
    1 - data bus can be configured as 8-, 16- or 32- bit depends on processor's bus size
    TX RAM Interface
    Interfaces to external dual port memories, used by the DMAC core to store transmitted frames.
    Synchronization logic
    There are 3 clock domains in the DMAC core. This module performs synchronization between these domains and assures correct data exchange between these domains.

    Transmit module
    Performs transmit management functions, sends frames to Ethernet medium. It is responsible for proper frame creation and response to PHY signals.