Digital Core Design

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DI2CSB

I2C Bus Interface Slave -Base version

The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many devices. The DI2CSB provides an interface between a passive target device e.g. memory, LCD display, pressure sensors etc. and an I2C bus. It can work as a slave receiver or as a transmitter - depending on the working mode determined by the master device. A very simple interface, composed with read, write and data signals, allows easy connection to target devices. The core does not require any programming and is ready to work after power up/reset. The read, write, burst read, burst write and repeated start transmissions are automatically recognized by the core. The core incorporates all features required by the I2C specification. The DI2CSB supports the following transmission modes: Standard, Fast, Fast Plus and High Speed.
The DI2CS is a technology independent design which can be implemented in a variety of process technologies.


Family summary

Design I2C specification Operation type Standard mode    Fast     mode Fast Plus mode High Speed mode Multi master 7 bit address 10 bit address Interrupt gen. Passive elements interface Microcontroller interface User defined timing
100 kb/s 400 kb/s 1 Mb/s 3.4 Mb/s
DI2CM v3.0 MASTER + + + + + + + + - + +
DI2CMS v3.0 MASTER/SLAVE + + + + + + + + - + +
DI2CS v3.0 SLAVE + + + + + + - + - + +
DI2CSB v3.0 SLAVE + + + + + + - - + - -

The main features of each I2C bus controllers family members have been summarized in table above. It gives a briefly member characterization helping you to find the most suitable IP Core for the application.

Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

Implementation Speed
grade
LUTs/
Slices
Frequency
[MHz]
SPARTAN 3 -5 73/50 218
SPARTAN 3E -5 73/50 213
SPARTAN 6 -3 48/33 336
VIRTEX 4 -12 76/48 467
VIRTEX 5 -2 57/30 487
VIRTEX 6 -3 43/23 515
VIRTEX 7 -3 50/23 478
KINTEX 7 -3 50/18 702
ARTIX 7 -3 43/17 478
VIRTEX UltraScale -3 48/7 500
ZYNQ-7000 -3 48/21 450

DI2CSB implementation results for XILINX devices. 
All features have been included. 

Implementation Speed
grade
Utilized Area
[LUT/PFU]
Frequency
[MHz]
XP -5 118/27 180
ECP -5 118/27 212
EC -5 118/27 203
ECP2 -7 78/42 317
ECP2M -7 70/27 318
SC -7 76/42 323
XP2 -7 70/27 263

DI2CSB implementation results for LATTICE devices. 
All features have been included. 

Implementation Speed
grade
Utilized Area
[LC]
Frequency
[MHz]
STRATIX -5 95 230
CYCLONE -6 95 195
STRATIX II -3 51 480
CYCLONE II -6 73 300
STRATIX III -2 50 730
CYCLONE III -6 68 430
STRATIX IV -2 49 740
CYCLONE IV -6 68 430

DI2CSB implementation results for ALTERA devices.
All features have been included. 


Key Features

  • Conforms to the latest I2C specification
  • Slave operation
    • Slave transmitter
    • Slave receiver
  • Supports 3 transmission speed modes
    • Standard (up to 100 kb/s)
    • Fast (up to 400 kb/s)
    • Fast Plus (up to 1 Mb/s)
    • High Speed (up to 3,4 Mb/s)
  • Allows operation from a wide range of input clock frequencies
  • Support for reads, writes, burst reads, burst writes, and repeated start
  • 7-bit addressing
  • No programming required
  • Simple interface allows easy connection to target device e.g. memory, LCD display, pressure sensors etc.
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready

Applications

  • Embedded microprocessor boards
  • Consumer and professional audio/video
  • Home and automotive radio
  • Low-power applications
  • Communication systems
  • Cost-effective reliable automotive systems

Symbol

 clk
 rst
 sdai
sdao 
 scli
 datai (7:0)
datao (7:0) 
rd 
wr 

Pins description

PinTypeDescription
clkinputGlobal clock
rstinputGlobal reset
sdaiinputI2C bus data line (input)
scliinputI2C bus clock line (input)
datai (7:0)inputData bus from target device
sdaooutputI2C bus data line (output)
datao (7:0)outputData bus to target device
rdoutputRead strobe for target device
wroutputWrite strobe for target device

Block Diagram

Data UnitIt controls SDA line, performs data and address shifts during the data transmission and reception. SDAI spikes are filtered by this unit.
sdai
sdao
Clock UnitSynchronizes data and address shifts during the data transmission and reception. SCLI spikes are filtered by this unit.
scli
Target device interfaceTarget device Interface performs the interface functions between DI2CSB internal blocks and target device. Allows easy connection of the core to a passive devices e.g. memory, LCD display, pressure sensors, I/O devices etc.
datai (7:0)
datao (7:0)
rd
wr
Control LogicControl Logic manages execution of all commands sent via interface. Synchronizes internal data flow.
clk
rst
DI2CSB data DI2CSB data bus

Units

Data Unit
It controls SDA line, performs data and address shifts during the data transmission and reception. SDAI spikes are filtered by this unit.
Clock Unit
Synchronizes data and address shifts during the data transmission and reception. SCLI spikes are filtered by this unit.
Target device interface
Target device Interface performs the interface functions between DI2CSB internal blocks and target device. Allows easy connection of the core to a passive devices e.g. memory, LCD display, pressure sensors, I/O devices etc.

Control Logic
Control Logic manages execution of all commands sent via interface. Synchronizes internal data flow.