Digital Core Design

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DI2CMS

I2C Bus Interface - Master/Slave

The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many devices. The DI2CMS core provides an interface between a microprocessor/microcontroller and an I2C bus. It can work as a master or a slave transmitter/receiver - depending on a working mode, determined by the microprocessor/microcontroller. The DI2CMS core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems and a high-speed transmission mode (the DI2CMS supports all the transmission speed modes). Built-in timer allows operation from a wide range of the clk frequencies.
The DI2CMS is technology independent, that's why a VHDL or VERILOG design can be implemented in a variety of process technologies. Furthermore, it can be also completely customized in accordance to the customer's needs.
The DI2CMS is delivered with fully automated testbench and complete set of tests, allowing easy package validation at each stage of SoC design flow.


Family summary

Design I2C specification Operation type Standard mode    Fast     mode Fast Plus mode High Speed mode Multi master 7 bit address 10 bit address Interrupt gen. Passive elements interface Microcontroller interface User defined timing
100 kb/s 400 kb/s 1 Mb/s 3.4 Mb/s
DI2CM v3.0 MASTER + + + + + + + + - + +
DI2CMS v3.0 MASTER/SLAVE + + + + + + + + - + +
DI2CS v3.0 SLAVE + + + + + + - + - + +
DI2CSB v3.0 SLAVE + + + + + + - - + - -

The main features of each I2C bus controllers family members have been summarized in table above. It gives a briefly member characterization helping you to find the most suitable IP Core for the application.

Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

Implementation Speed
grade
Utilized Area
[LUT/PFU]
Frequency
[MHz]
XP -5 477 / 153 148
EC -5 477 / 153 166
ECP -5 477 / 153 167
ECP2 -7 421 / 153 245
SC -7 415 / 156 284

DI2CMS implementation results for LATTICE devices.
All features have been included. 

Implementation Speed
grade
LUTs/
Slices
Frequency
[MHz]
SPARTAN 3 -5 424/286 161
SPARTAN 3E -5 417/285 166
SPARTAN 6 -3 289/119 269
VIRTEX 4 -12 464/290 310
VIRTEX 5 -2 313/173 382
VIRTEX 6 -3 290/93 375
VIRTEX 7 -3 324/109 492
KINTEX 7 -3 321/129 511
ARTIX 7 -3 292/119 329

DI2CMS implementation results for XILINX devices.
All features have been included. 

Implementation Speed
grade
Utilized Area
[LC]
Frequency
[MHz]
MAX3000A -7 198 49
MAX7000AE -5 198 67
MAX 2 -3 291 187
APEX20KC -7 394 150
CYCLONE -6 370 220
STRATIX -5 291 254
CYCLONE II -6 354 263
STRATIX II -3 337 380

DI2CMS implementation results for ALTERA devices.
All features have been included. 


Info

The I2C-bus supports any IC fabrication process (NMOS, CMOS, bipolar). Two wires, serial data (SDA) and serial clock (SCL), carry information between devices connected to the bus. Each devices is recognised by a unique address – whether it is a microcontroller, LCD driver, memory or keyboard interface. It can operate as either  transmitter or receiver, depending on the function of the device. Obviously an LCD driver is only a receiver, whereas a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers (see Figures below).

A master is the device which initiates a data transfer on the bus and generates the SCL clock signals. A slave is the device addressed by a master.
The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually microcontrollers or microprocessors.

Key Features

  • Conforms to v.3.0 of the I2C specification
  • Master mode
    • Master operation
      • Master transmitter
      • Master receiver
    • Support for all transmission speeds
      • Standard (up to 100 kb/s)
      • Fast (up to 400 kb/s)
      • Fast Plus (up to 1 Mb/s)
      • High Speed (up to 3,4 Mb/s)
    • Arbitration and clock synchronization
    • Support for multi-master systems
    • Support for both 7-bit and 10-bit addressing formats on the I2C bus
    • Build-in 8-bit timer for data transfers speed adjusting
  • Slave mode
    • Slave operation
      • Slave transmitter
      • Slave receiver
    • Supports 3 transmission speed modes
      • Standard (up to 100 kb/s)
      • Fast (up to 400 kb/s)
      • Fast Plus (up to 1 Mb/s)
      • High Speed (up to 3,4 Mb/s)
    • Allows operation from a wide range of input clock frequencies
    • User-defined data setup time
  • User-defined timing (data setup, start setup, start hold, etc.)
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Interrupt generation
  • Available system interface wrappers:
    • AMBA - APB Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready

Applications

  • Embedded microprocessor boards
  • Consumer and professional audio/video
  • Home and automotive radio
  • Low-power applications
  • Communication systems
  • Cost-effective reliable automotive systems

Symbol

 rst
 clk
 scli
sclo 
sclhs 
 sdai
sdao 
 we
 rd
 cs
 datai (7:0)
 address (2:0)
irq 
datao (7:0) 

Pins description

PinTypeDescription
rstinputGlobal reset
clkinputGlobal clock
scliinputI2C bus clock line (input)
sdaiinputI2C bus data line (input)
weinputProcessor write strobe
rdinputProcessor read strobe
csinputChip select
datai (7:0)inputProcessor data bus (input)
address (2:0)inputProcessor address lines
sclooutputI2C bus clock line (output)
sclhsoutputHigh-speed clock line (output)
sdaooutputI2C bus data line (output)
irqoutputProcessor interrupt line
datao (7:0)outputProcessor data bus (output)

Block Diagram

TimerTimer allows operation from a wide range of the input frequencies. It is programmed by an user before transmission and can be reprogrammed to change the SCL frequency.
Clock UnitPerforms clock synchronization, clock generation in master mode, and clock stretching in slave mode.
scli
sclo
sclhs
Control LogicControl Logic manages execution of all commands sent via interface. Synchronizes internal data flow. Includes Control Register used for performing all types of I2C Bus transmissions, and Status Register indicates state of the I2C Bus and the DI2CMS core.
Data UnitIt controls SDA line, performs data and address shifts during the data transmission and reception. Input data spikes are also filtered.
sdai
sdao
CPU interfaceCPU Interface performs the interface functions between DI2CMS internal blocks and microprocessor. It allows an easy connection of the core to the microprocessor/microcontroller system.
we
rd
cs
irq
datai (7:0)
datao (7:0)
address (2:0)
rst
clk
data bus

Units

Timer
Timer allows operation from a wide range of the input frequencies. It is programmed by an user before transmission and can be reprogrammed to change the SCL frequency.
Clock Unit
Performs clock synchronization, clock generation in master mode, and clock stretching in slave mode.
Control Logic
Control Logic manages execution of all commands sent via interface. Synchronizes internal data flow. Includes Control Register used for performing all types of I2C Bus transmissions, and Status Register indicates state of the I2C Bus and the DI2CMS core.

Data Unit
It controls SDA line, performs data and address shifts during the data transmission and reception. Input data spikes are also filtered.
CPU interface
CPU Interface performs the interface functions between DI2CMS internal blocks and microprocessor. It allows an easy connection of the core to the microprocessor/microcontroller system.