Digital Core Design

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DI2CM

I2C Bus Interface - Master

The I2C is a two-wire, bi-directional serial bus, which provides simple and efficient method of short distance data transmission between many devices. The DI2CM core provides an interface between a microprocessor/microcontroller and the I2C bus. It can work as a master transmitter or a master receiver - depending on a working mode, determined by the microprocessor/microcontroller. The DI2CM core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems and high-speed transmission mode. Built-in timer allows operation from a wide range of the clk frequencies.
The DI2CM is a technology independent design, that can be implemented in a variety of process technologies.


Family summary

Design I2C specification Operation type Standard mode    Fast     mode Fast Plus mode High Speed mode Multi master 7 bit address 10 bit address Interrupt gen. Passive elements interface Microcontroller interface User defined timing
100 kb/s 400 kb/s 1 Mb/s 3.4 Mb/s
DI2CM v3.0 MASTER + + + + + + + + - + +
DI2CMS v3.0 MASTER/SLAVE + + + + + + + + - + +
DI2CS v3.0 SLAVE + + + + + + - + - + +
DI2CSB v3.0 SLAVE + + + + + + - - + - -

The main features of each I2C bus controllers family members have been summarized in table above. It gives a briefly member characterization helping you to find the most suitable IP Core for the application.

Key Features

  • Conforms to v.3.0 of the I2C specification
  • Master operation
    • Master transmitter
    • Master receiver
  • Support for all transmission speeds
    • Standard (up to 100 kb/s)
    • Fast (up to 400 kb/s)
    • Fast Plus (up to 1 Mb/s)
    • High Speed (up to 3,4 Mb/s)
  • Arbitration and clock synchronization
  • Support for multi-master systems
  • Support for both 7-bit and 10-bit addressing formats on the I2C bus
  • Interrupt generation
  • Build-in 8-bit timer for data transfers speed adjusting
  • Host side interface dedicated for microprocessors/microcontrollers
  • User-defined timing (data setup, start setup, start hold, etc.)
  • Available system interface wrappers:
    • AMBA - APB Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready

Applications

  • Embedded microprocessor boards
  • Consumer and professional audio/video
  • Home and automotive radio
  • Low-power applications
  • Communication systems
  • Cost-effective reliable automotive systems

Symbol

 rst
 clk
 scli
sclo 
sclhs 
 sdai
sdao 
 datai (7:0)
 rd
 we
 address (1:0)
 cs
datao (7:0) 
irq 

Pins description

PinTypeDescription
rstinputGlobal reset
clkinputGlobal clock
scliinputI2C bus clock line (input)
sdaiinputI2C bus data line (input)
datai (7:0)inputProcessor data bus (input)
rdinputProcessor read strobe
weinputProcessor write strobe
address (1:0)inputProcessor address lines
csinputChip select
sclooutputI2C bus clock line (output)
sclhsoutputHigh-speed clock line (output)
sdaooutputI2C bus data line (output)
datao (7:0)outputProcessor data bus (output)
irqoutputProcessor interrupt line

Block Diagram

TimerTimer allows operation from a wide range of the input frequencies. It is programmed by user before transmission and can be reprogrammed to change the SCL frequency.
Clock UnitClock Unit performs generation of the serial SCL clock. It is responsible for input spike filtering, clock synchronization and arbitration during operations in multi-master systems.
scli
sclo
sclhs
Control LogicControl Logic manages execution of all commands sent via interface. Synchronizes internal data flow. Includes Control Register used for performing all types of I2C Bus transmissions, and Status Register indicates state of the I2C Bus and the DI2CM core.
Data UnitIt controls SDA line, performs data and address shifts during the data transmission and reception. Input data spikes are also filtered.
sdai
sdao
CPU InterfaceCPU Interface performs the interface functions between DI2CM internal blocks and microprocessor. Allows easy connection of the core to a microprocessor/microcontroller system.
datai (7:0)
datao (7:0)
rd
we
address (1:0)
cs
irq
rst
clk
DI2CM data DI2CM data bus

Units

Timer
Timer allows operation from a wide range of the input frequencies. It is programmed by user before transmission and can be reprogrammed to change the SCL frequency.
Clock Unit
Clock Unit performs generation of the serial SCL clock. It is responsible for input spike filtering, clock synchronization and arbitration during operations in multi-master systems.
Control Logic
Control Logic manages execution of all commands sent via interface. Synchronizes internal data flow. Includes Control Register used for performing all types of I2C Bus transmissions, and Status Register indicates state of the I2C Bus and the DI2CM core.

Data Unit
It controls SDA line, performs data and address shifts during the data transmission and reception. Input data spikes are also filtered.
CPU Interface
CPU Interface performs the interface functions between DI2CM internal blocks and microprocessor. Allows easy connection of the core to a microprocessor/microcontroller system.