Digital Core Design

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DUSB2

USB 2.0 Device Controller

The DUSB2 is hardware implementation of full/high-speed peripheral controller that interfaces to the UTMI bus transceiver. The DUSB2 contains the USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic. The DUSB2 is designed to support 12 Mb/s "Full Speed" (FS) and 480 Mb/s "High Speed" (HS) serial data transmission rates. The design is technology independent and thus can be implemented in a variety of process technologies. This core strictly conforms to the USB Specification v2.0. The DUSB2 core is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow.


Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

Implementation Speed
grade
Utilized Area
[Slices]
Frequency
[MHz]
SC -7 940 270/>100
ECP2 -7 1030 190/>100
ECP2M -7 1030 170/>100
XP2 -7 1160 160/>100

Implementation results of the DUSB2 core suitable for HID and Mass Storage applications in LATTICE devices.

Implementation Speed
grade
LUTs/
Slices
Frequency
[MHz]
SPARTAN-III -5 1671/1310 121
SPARTAN-IIIE -5 1694/1327 135
SPARTAN-VI -3 1420/548 212
VIRTEX-IV -12 1701/1328 256
VIRTEX-V -2 1423/810 300
VIRTEX-VI -3 1412/682 312
VIRTEX-VII -3 1483/722 384
KINTEX-VII -3 1492/704 384
ARTIX-VII -3 1388/695 263
VIRTEX UltraScale -3 1233/262 500
ZYNQ-7000 -3 1232/482 330

Implementation results of the DUSB2 core suitable for HID and Mass Storage applications in XILINX devices.

Implementation Speed
grade
Utilized Area
[LC]
Frequency
[MHz]
CYCLONE-II -6 1890 150/>100
CYCLONE-III -6 1890 180/>100
STRATIX-II -3 1270 250/>100
STRATIX-III -2 1270 270/>100
Arria GX -6 1890 200/>100

Implementation results of the DUSB2 core suitable for HID and Mass Storage applications in ALTERA devices.


Key Features

  • Full compliance with the USB 2.0 specification
  • Full-speed 12 Mbps operation
  • High-speed 480 Mbps operation
  • Software configurable EP0 control endpoint size 8-64 bytes
  • Software configurable 15 IN/OUT end-points:
    • configurable number of endpoints
    • configurable type of each endpoint: INTERRUPT, BULK or ISOCHRONOUS
    • configurable direction of each endpoint
    • configurable size of each endpoint: 8-1024 bytes
  • Supports UTMI Transceiver Macrocell Interface
  • Synchronous RAM interface for FIFOs
  • Suspend and resume power management functions
  • Simple interface allows easy connection to CPU
  • Allows operation from a wide range of CPU clock frequencies
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking
  • No internal tri-states
  • Lite design, small gate count and fast operation
  • Scan test ready

Applications

  • Human Interface Devices like keyboards, mouse or game peripherals
  • Mass Storage devices like flash disk, mp3 or mp4 player
  • GPS navigation system
  • Digital Camera
  • Cellular phone
  • Audio devices like microphone or speakers
  • Printer
  • Scanner

Symbol

 utmiclk
 utmilinestate (1:0)
 utmidatai (7:0)
 utmirxvalid
 utmirxactive
 utmirxerror
 utmitxready
utmiopmode (1:0) 
utmidatao (7:0) 
utmitxvalid 
utmisuspendm 
utmixcvrselect 
utmitermselect 
 cpuclk
 cpuaddress (7:0)
 cpudatai (7:0)
 cpuwr
 cpurd
cpudatao (7:0) 
irq 
 sramdataia (7:0)
 sramdataib (7:0)
sramaddra (13:0) 
sramaddrb (13:0) 
sramdataoa (7:0) 
sramdataob (7:0) 
sramwea 
sramweb 

Pins description

PinTypeDescription
utmiclkinputUSB clock
utmilinestate (1:0)inputUSB line state
utmidatai (7:0)inputUSB parallel data input bus
utmirxvalidinputUSB receive valid
utmirxactiveinputUSB receive active
utmirxerrorinputUSB receive error
utmitxreadyinputUSB transmit ready
cpuclkinputCPU clock
cpuaddress (7:0)inputCPU address bus
cpudatai (7:0)inputCPU data input bus
cpuwrinputCPU write
cpurdinputCPU read
sramdataia (7:0)inputSRAM port A data input bus
sramdataib (7:0)inputSRAM port B data input bus
utmiopmode (1:0)outputUSB operational mode
utmidatao (7:0)outputUSB parallel data output bus
utmitxvalidoutputUSB transmit valid
utmisuspendmoutputUSB suspend
utmixcvrselectoutputUSB transceiver select
utmitermselectoutputUSB termination select
cpudatao (7:0)outputCPU data output bus
irqoutputCPU interrupt request
sramaddra (13:0)outputSRAM port A address bus
sramaddrb (13:0)outputSRAM port B address bus
sramdataoa (7:0)outputSRAM port A data output bus
sramdataob (7:0)outputSRAM port B data output bus
sramweaoutputSRAM port A write enable
sramweboutputSRAM port B write enable

Block Diagram

UTMI interfaceThe UTMI interface is clocked by utmiclk clock and manages communication with USB 2.0 Transceiver Macrocell. It is responsible for reset detection, speed handshake, token, data and handshake packet reception and transmission.
utmiclk
utmilinestate (1:0)
utmidatai (7:0)
utmirxvalid
utmirxactive
utmirxerror
utmitxready
utmiopmode (1:0)
utmidatao (7:0)
utmitxvalid
utmisuspendm
utmixcvrselect
utmitermselect
CPU interfaceThe CPU interface module is clocked by cpuclk clock and manages communication with some CPU. In this module DUSB2 core configuration and status registersare are being located .
cpuclk
cpuaddress (7:0)
cpudatai (7:0)
cpuwr
cpurd
cpudatao (7:0)
irq
SRAM interfaceThe SRAM interface module manages communication with Synchronous Random Access Memory. It generates address, read and write signals for the SRAM memory and buffers data bytes during the FIFO read and write operations.
sramdataia (7:0)
sramdataib (7:0)
sramaddra (13:0)
sramaddrb (13:0)
sramdataoa (7:0)
sramdataob (7:0)
sramwea
sramweb
EP0Special bidirectional endpoint used for device configuration. Allows generic USB control and status access.
EP1Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP2Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP3Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP4Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP5Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP6Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP7Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP8Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP9Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP10Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP11Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP12Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP13Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP14Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP15Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

Units

UTMI interface
The UTMI interface is clocked by utmiclk clock and manages communication with USB 2.0 Transceiver Macrocell. It is responsible for reset detection, speed handshake, token, data and handshake packet reception and transmission.
CPU interface
The CPU interface module is clocked by cpuclk clock and manages communication with some CPU. In this module DUSB2 core configuration and status registersare are being located .
SRAM interface
The SRAM interface module manages communication with Synchronous Random Access Memory. It generates address, read and write signals for the SRAM memory and buffers data bytes during the FIFO read and write operations.

EP0
Special bidirectional endpoint used for device configuration. Allows generic USB control and status access.
EP1
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP2
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP3
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP4
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP5
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP6
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP7
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP8
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP9
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP10
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP11
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP12
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP13
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.
EP14
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.

EP15
Unidirectional, configurable data endpoint used for application specific data transmission. Supports INTERRUPT, BULK and ISOCHRONOUS transfers.