Digital Core Design

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DF6808

8-bit FAST Microcontrollers Family

The DF6808 is an advanced, 8-bit, MCU IP Core, with highly sophisticated, on chip peripheral capabilities. The DF6808 soft core is binary-compatible with the industry standard Motorola 68HC08 8-bit microcontroller. It can achieve a performance of 45 - 100 million instructions per second.
The DF6808 has a FAST architecture, that is 3.2 times faster, compared to original implementation. In the standard configuration, the core has integrated on chip, major peripheral functions.
The DF6808 Microcontroller Core contains full-duplex UART- Asynchronous Serial Communication Interface (SCI) and the Synchronous Serial Peripheral Interface (SPI).
The main 16-bit, free-running timer system, has two input capture lines and two output-compare lines.
Self-monitoring circuitry is included on-chip, to protect against system errors. The Computer Operating Properly (COP) watchdog system, protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt, if illegal opcode is detected.
Two software-controlled power-saving modes - WAIT and STOP, are available to conserve additional power. These modes make the DF6808 IP Core especially attractive, for automotive and battery-driven applications.
DF6808 is fully customizable - it is delivered in the exact configuration, to meet user's requirements. There is no need to pay extra, for unused features and wasted silicon. It includes fully automated testbench with complete set of tests, allowing easy package validation, at each stage of SoC design flow.

Each DCD's DF68XX Core, has built-in support for DCD Hardware Debug System called DoCDTM. It's a real-time hardware debugger provides debugging capability of a whole System on Chip (SoC).

Unlike the other on-chip debuggers DoCDTM, which provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories. More details about DCD on Chip Debugger


Family summary

Family IP Core Architecture
type
Memory space DoCDTM UART (SCI) SPI M/S IO Ports Watchdog
Timer
Timer Compare / Capture Pulse
accumulator
READY
pin
Chip Selects Gatecount
HC05, HC08 DF6805 fast 64k + + - 4 + 1 2/2 - + - 7000
- DF6808 fast 64k + + - 4 + 1 2/2 - + - 8300
- D68HC05 legacy 64k + + + 4 + 1 1/1 - - - -
- D68HC08 legacy 64K + + + 4 + 1 2/1 - - - 10000
HC11 DF6811E fast 64k + + + 5 + 1 5/4 + + - 12000
- DF6811F fast 64k + + + 7 + 1 5/4 + + - 14000
- DF6811K fast 1M + + + 10 + 3 13/6 + + - 21000
- D68HC11E legacy 64k + + + 5 + 1 5/4 + - - 13000
- D68HC11K legacy 1M + + 1 10 + 3 13/6 + - 4 21000
- D68HC11F legacy 64k + + + 7 + 1 5/4 - - 4 13500
6802, 6803 DF6802 fast 64k + - - - - - - - - - -
- DF6803 fast 64k + + + 4 - 1 + - - - -
- D6802 legacy 64k + - - - - - - - - - 3600
- D6803 legacy 64k + + + 4 - 1 + - - - 6000

The main features of each D68XX and DF68XX family member, have been summarized in the table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and request the core modifications.

Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

Implementation Speed
grade
Utilized Area
[LUT/PFU]
Frequency
[MHz]
EC -5 2857/651 45
ECP -5 2857/651 45
XP -5 2857/651 43

DF6808 implementation results for LATTICE devices. The CPU features and Peripherals have been included. 

Implementation Speed
grade
Utilized Area
[Slices]
Frequency
[MHz]
SPARTAN-IIE -7 1701 36
SPARTAN-III -5 1699 44
SPARTAN-IIIE -4 1716 35
VIRTEX-E -8 1689 37
VIRTEX-II -6 1696 68
VIRTEX-II pro -7 1672 77
VIRTEX-IV -12 1686 87

DF6808 implementation results for XILINX devices. The CPU features and Peripherals have been included. 

Implementation Speed
grade
Utilized Area
[LC]
Frequency
[MHz]
APEX20KC -7 2531 48
CYCLONE -6 2635 61
CYCLONE II -6 2635 65
STRATIX -5 2136 65
STRATIX II -3 2124 96
STRATIX GX -5 2636 66

DF6808 implementation results for ALTERA devices. All features have been included. 


CPU Features


Symbol

 clk
 rst
halt 
 docddatai
 clkdocd
docddatao 
docdclk 
 mosi
 miso
 ss
 sck
sso (7:0) 
 ready
 prgdata (7:0)
 datai (7:0)
 ufrdatai (7:0)
prgaddr (15:0) 
prgoe 
datao (7:0) 
addr (15:0) 
ramwe 
ramoe 
ufraddr (5:0) 
ufrwe 
ufroe 
 irq
 cap2
 cap1
cmp1 
cmp2 
 portai (7:0)
 portbi (7:0)
 portci (7:0)
 portdi (7:0)
portao (7:0) 
portbo (7:0) 
portco (7:0) 
portdo (7:0) 
ddra (7:0) 
ddrb (7:0) 
ddrc (7:0) 
ddrd (7:0) 
 rxd
txd 

Pins description

PinTypeDescription
clkinputGlobal clock
rstinputGlobal reset
docddataiinputDoCDTM serial data input
clkdocdinputClock signal to DoCDTM On chip Debugger module. This separate clock line allow DoCDTM to operate during the SLEEP mode (major clock CLK is stopped).
mosiinputSPI Master Output - Slave input
misoinputSPI Master input - Slave output
ssinputSPI slave select
sckinputSPI clock line
readyinputREADY pin allows CPU to operate with slow program and data memories. HIGH state on READY pin drives CPU to the WAIT state.
prgdata (7:0)inputProgram memory data bus input. (used in Harvard architectue only)
datai (7:0)inputData/Program memory data bus input
ufrdatai (7:0)inputExternal UFR registers data bus input
irqinputExternal interrupt request input
cap2inputInput capture channel 2 input
cap1inputInput capture channel 1 input
portai (7:0)inputPort A input
portbi (7:0)inputPort B input
portci (7:0)inputPort C input
portdi (7:0)inputPort D input
rxdinputSCI receiver data input
haltoutputHalt clock system during STOP Instruction
docddataooutputDoCDTM serial data output
docdclkoutputDoCDTM serial data clock line
sso (7:0)outputSlave Select outputs
prgaddr (15:0)outputProgram memory address bus. (used in Harvard architecture only)
prgoeoutputProgram memory output enable.
datao (7:0)outputData memory and External UFR registers output data bus
addr (15:0)outputData memory address bus
ramweoutputData memory write enable
ramoeoutputData memory output enable
ufraddr (5:0)outputExternal UFR registers address bus
ufrweoutputExternal UFR registers write enable
ufroeoutputExternal UFR registers output enable
cmp1outputOutput compare channel 1 output
cmp2outputOutput compare channel 2 output
portao (7:0)outputPort A output
portbo (7:0)outputPort B output
portco (7:0)outputPort C output
portdo (7:0)outputPort D output
ddra (7:0)outputPort A data direction control
ddrb (7:0)outputPort B data direction control
ddrc (7:0)outputPort C data direction control
ddrd (7:0)outputPort D data direction control
txdoutputSCI transmitter data output

Block Diagram

Opcode DecoderPerforms an opcode decoding instruction and control functions for all other blocks.
Control UnitControl Unit performs the core synchronization and data flow control. This module manages execution of all instructions. The STOP instruction and waking up the processor from the STOP mode.
halt
DoCDTM DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurs at particular address, with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
The separate DoCDTM clock line, allows debugger to operate in the SLEEP mode (major clock line CLK is stopped).
docddatai
docddatao
docdclk
clkdocd
SPI UnitIt is a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communication in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough, to interface directly with numerous standard product peripherals, from several manufacturers. Data transfer rate up to CLK/4. Clock control logic allows to select the clock polarity and to choose the two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included, to support interprocessor communications. A write-collision detector indicates, when an attempt is made, to write data to the serial shift register, while the transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers, if more than one SPI device simultaneously attempts to become bus master.
mosi
miso
ss
sck
sso (7:0)
ALUArithmetic Logic Unit performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (A), Condition Code Register (CCREG), Index registers (H:X) and related logic, such as arithmetic unit, logic unit, multiplier and divider.
Bus ControllerProgram Memory, Data Memory and SFR's (Special Function Register) interface - controls access into the program and data memories and special registers. It contains Program Counter (PC), Stack Pointer (SP) register and related logic.
ready
prgdata (7:0)
prgaddr (15:0)
prgoe
datai (7:0)
datao (7:0)
addr (15:0)
ramwe
ramoe
ufrdatai (7:0)
ufraddr (5:0)
ufrwe
ufroe
Interrupt ControllerThe extended Interrupt Controller has implemented 7-level interrupt priority control. The interrupt requests may come from the external pin (IRQ) and also from particular peripherals. The peripheral systems generate maskable interrupts, which are recognized only, if the global interrupt mask bit (I) in the CCR is cleared. Maskable interrupts are prioritized in accordance to default arrangement, established during reset. When an interrupt condition occurs, the interrupt status flag is set, to indicate the condition.
irq
Watchdog TimerThe Watchdog Timer consist of free running timer CLK/213 and control logic. The Watchdog Timer can be enabled by the software, by writing "1" to the WDOG Bit in MISC ($0C) register. Once enabled, the WDT timer cannot be disabled by the software. In addition, the WDOG bit acts as a reset mechanism for the WDT Timer. Writing "1" to the WDOG Bit, clears WDT counter and inhibits Watchdog timeout.
Timer with Compare CaptureThe programmable timer is based on free-running, 16-bit counter, plus input capture/output compare circuitry. The timer can be used for many purposes, including measuring pulse length of two input signals and generating two output signals. The timer has a 16-bit architecture, hence each specific functional segment is represented by two 8-bit registers. These registers contain the high and the low byte of that functional block. Accessing the low byte of a specific timer function, allows full control of that function, however, an access of the high byte, inhibits that specific timer function, until the byte is also accessed. Each of the input-capture channel, has its own 16-bit time capture latch (input-capture register) and each of the output-compare channels, has its own, 16-bit compare register. Additional control bits permit software to control the edge(s), that trigger each input-capture function and the automatic actions, that result from output-compare functions. Although hardwired logic is included to automate many timer activities, this timer architecture is essentially a software-oriented system. This structure is easily adaptable to a very wide range of applications (although for some specific timing applications it is not as efficient, as a dedicated hardware)
cap2
cmp1
cmp2
cap1
IOPortsAll ports are 8-bit general-purpose bi-directional I/O system. The PORTA, PORTB, PORTC, PORTD data registers, have their corresponding data direction registers - DDRA, DDRB, DDRC, DDRD, to control ports data flow. It ensures, that all ports have full I/O selectable registers. Writes to any ports pins cause data to be stored in the data registers. If any port pins are configured as output, then data registers are driven out of those pins. Reads from port pins configured as input, cause the input pin read. If port pins is configured as output, during read data register is read.
Writes to any ports pins, not configured as outputs, do not cause data to be driven out of those pins but the data is stored in the output registers. Thus, if the pins later become outputs, the last data written to port will be driven out of the port pins.
portai (7:0)
portbi (7:0)
portci (7:0)
portdi (7:0)
portao (7:0)
portbo (7:0)
portco (7:0)
portdo (7:0)
ddra (7:0)
ddrb (7:0)
ddrc (7:0)
ddrd (7:0)
SCIThe SCI is a full-duplex UART type asynchronous system, using standard, non return to zero (NRZ) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. The Core resynchronizes the receiver bit clock on all, one to zero transitions in the bit stream. The differences in baud rate, between the sending device and the SCI, are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time and majority logic decides the sense for the bit. For the start and stop bits, seven logic samples are taken. Even if the noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver has also the ability to enter a temporary standby mode (called receiver wakeup), to ignore messages intended for a different receiver. Logic automatically wakes up the receiver, in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multidrop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual Transmit Data Register Empty (TDRE) status flag, this SCI also provides a Transmit Complete (TC) indication, that can be used in applications with a modem.
rxd
txd
clk
rst
Data bus Internal 8-bit data bus.
SFR data bus 8-bit Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture.

Units

Opcode Decoder
Performs an opcode decoding instruction and control functions for all other blocks.
Control Unit
Control Unit performs the core synchronization and data flow control. This module manages execution of all instructions. The STOP instruction and waking up the processor from the STOP mode.
DoCDTM
DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurs at particular address, with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
The separate DoCDTM clock line, allows debugger to operate in the SLEEP mode (major clock line CLK is stopped).

SPI Unit
It is a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communication in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough, to interface directly with numerous standard product peripherals, from several manufacturers. Data transfer rate up to CLK/4. Clock control logic allows to select the clock polarity and to choose the two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included, to support interprocessor communications. A write-collision detector indicates, when an attempt is made, to write data to the serial shift register, while the transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers, if more than one SPI device simultaneously attempts to become bus master.
ALU
Arithmetic Logic Unit performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (A), Condition Code Register (CCREG), Index registers (H:X) and related logic, such as arithmetic unit, logic unit, multiplier and divider.
Bus Controller
Program Memory, Data Memory and SFR's (Special Function Register) interface - controls access into the program and data memories and special registers. It contains Program Counter (PC), Stack Pointer (SP) register and related logic.

Interrupt Controller
The extended Interrupt Controller has implemented 7-level interrupt priority control. The interrupt requests may come from the external pin (IRQ) and also from particular peripherals. The peripheral systems generate maskable interrupts, which are recognized only, if the global interrupt mask bit (I) in the CCR is cleared. Maskable interrupts are prioritized in accordance to default arrangement, established during reset. When an interrupt condition occurs, the interrupt status flag is set, to indicate the condition.
Watchdog Timer
The Watchdog Timer consist of free running timer CLK/213 and control logic. The Watchdog Timer can be enabled by the software, by writing "1" to the WDOG Bit in MISC ($0C) register. Once enabled, the WDT timer cannot be disabled by the software. In addition, the WDOG bit acts as a reset mechanism for the WDT Timer. Writing "1" to the WDOG Bit, clears WDT counter and inhibits Watchdog timeout.
Timer with Compare Capture
The programmable timer is based on free-running, 16-bit counter, plus input capture/output compare circuitry. The timer can be used for many purposes, including measuring pulse length of two input signals and generating two output signals. The timer has a 16-bit architecture, hence each specific functional segment is represented by two 8-bit registers. These registers contain the high and the low byte of that functional block. Accessing the low byte of a specific timer function, allows full control of that function, however, an access of the high byte, inhibits that specific timer function, until the byte is also accessed. Each of the input-capture channel, has its own 16-bit time capture latch (input-capture register) and each of the output-compare channels, has its own, 16-bit compare register. Additional control bits permit software to control the edge(s), that trigger each input-capture function and the automatic actions, that result from output-compare functions. Although hardwired logic is included to automate many timer activities, this timer architecture is essentially a software-oriented system. This structure is easily adaptable to a very wide range of applications (although for some specific timing applications it is not as efficient, as a dedicated hardware)

IOPorts
All ports are 8-bit general-purpose bi-directional I/O system. The PORTA, PORTB, PORTC, PORTD data registers, have their corresponding data direction registers - DDRA, DDRB, DDRC, DDRD, to control ports data flow. It ensures, that all ports have full I/O selectable registers. Writes to any ports pins cause data to be stored in the data registers. If any port pins are configured as output, then data registers are driven out of those pins. Reads from port pins configured as input, cause the input pin read. If port pins is configured as output, during read data register is read.
Writes to any ports pins, not configured as outputs, do not cause data to be driven out of those pins but the data is stored in the output registers. Thus, if the pins later become outputs, the last data written to port will be driven out of the port pins.
SCI
The SCI is a full-duplex UART type asynchronous system, using standard, non return to zero (NRZ) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. The Core resynchronizes the receiver bit clock on all, one to zero transitions in the bit stream. The differences in baud rate, between the sending device and the SCI, are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time and majority logic decides the sense for the bit. For the start and stop bits, seven logic samples are taken. Even if the noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver has also the ability to enter a temporary standby mode (called receiver wakeup), to ignore messages intended for a different receiver. Logic automatically wakes up the receiver, in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multidrop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual Transmit Data Register Empty (TDRE) status flag, this SCI also provides a Transmit Complete (TC) indication, that can be used in applications with a modem.