Digital Core Design

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D85C30

UART Core with SDLC Function

    UART IP Core with SDLC Function

    The D85C30 - (Serial Communication Controller) is a dual channel USART (Universal Synchronous/Asynchronous Receiver/Transmitter) device, designed for use with 8 and 16-bit microprocessors. It functions as serial-to-parallel, parallel-to-serial converter/controller and can be software-configured to satisfy a wide variety of serial communications applications. The device contains a variety of new, sophisticated internal functions, including on-chip baud rate generators. The D85C30 handles asynchronous formats, synchronous byte-oriented protocols, such as IBM® Bisync, and synchronous bit-oriented protocols, like HDLC and IBM SDLC. This versatile device supports virtually any serial data transfer application (telecommunication, LAN, etc.). The device can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The D85C30 has also facilities for modem control in both channels. In applications where these controls are not needed, modem controls can be used for general-purpose I/O. The D85C30 can be configured by user to handle all synchronous formats, regardless of data size, number of stop bits or parity requirements. The D85C30 is controlled through access to 14 Write registers and 7 Read registers per channel (the number of the registers varies depending on the version). Within each operating mode, the D85C30 also allows for protocol variations by checking odd or even parity bits, character insertion or deletion, CRC generation, checking break and abort generation and detection, and many other protocol-dependent features.


    Performance

    D85C30 has been tested in variety of FPGA and ASIC technologies.

    Implementation Logic Cells MEMORY
    Bits
    Frequency [MHz]
    ARIA 2033/943 608 83
    ARIA II 1954/943 608 167
    ARIA V 1966/1052 608 118
    CYCLONE 2730 608 68
    CYCLONE II 2883 608 90
    CYCLONE III 2896 608 109
    CYCLONE IV E 2869 608 112
    CYCLONE IV 6X 2881 608 112
    CYCLONE V 1967 608 89
    STRATIX 2730 608 72
    STRATIX II 2037 608 123
    STRATIX III 1962/997 608 214
    STRATIX IV 1952/997 608 196
    STRATIX V 1950/1044 608 219

    D85C30 implementation results for ALTERA devices.
    All features have been included.

    Implementation LUTs/Slices MEMORY
    Blocks
    Frequency [MHz]
    Artix 7 1785/797 2 165
    Kintex 7 1877/676 2 239
    Zynq 1868/774 2 171
    Virtex 7 1869/878 2 194
    Virtex 6 1801/850 2 144
    Virtex 5 1861/846 2 161
    Virtex 4 2533/1598 2 121
    Spartan 6 1815/681 2 122
    Spartan 3E 2647/1655 2 75
    Spartan 3 2625/1645 2 72

    D85C30 implementation results for XILINX devices.
    All features have been included.


    Key Features

    • Software compatible with Z85C30
    • Dual Channel: A, B
    • Configuration capability
    • Asynchronous mode:
      • Asynchronous (x16, x32, or x64 clock
      • Isochronous (x1 clock)
    • Character-Oriented mode:
      • Monosynchronous
      • Bisynchronous
      • External Synchronous
    • Bit-Oriented mode:
      • SDLC/HDLC
      • SDLC/HDLC Loop
    • Complete status reporting capabilities
    • Receiver data FIFO and Error FIFO
    • SDLC Frame FIFO
    • Data encoder\decoder:
      • NRZ, NRZI
      • FM0, FM1
      • Manchester (require external logic)
    • Line break generation and detection
    • Internal diagnostic capabilities:
      • Loop-back controls for communications link fault isolation
      • Auto Echo
      • Break, parity, overrun, framing error simulation
    • Fully synchronous design with no internal tristate buffers

    Applications

    • Serial Data communications applications
    • Modem interface
    • Embedded microprocessor boards