Digital Core Design

The Power of Intellectual Property

The DF6802 is a 8-bit synthesisable MPU IP Core, software-compatible with the Motorola MC6802. The DF6802 has an enhanced internal architecture, which allows it to execute the code approximately 4 times faster than original 6802 running at the same clock frequency.
Two software-controlled power-saving modes - WAIT and HALT, are available to conserve additional power. These modes make the DF6802 IP Core especially attractive, for automotive and battery-driven applications.
The DF6802 has built-in real time hardware on chip debugger DoCDTM, allowing easy software debugging and validation.
The DF6802 is fully customizable - it is delivered in the exact configuration, to meet user's requirements. There is no need to pay extra, for not used features and wasted silicon. It includes fully automated testbench with complete set of tests, allowing easy package validation, at each stage of SoC design flow.

Each of the DCD's D68XX Core has a built-in support for DCD Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCDTM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microprocessor. More details about DCD on Chip Debugger


Family summary

Family IP Core Architecture
type
Memory space DoCDTM UART (SCI) SPI M/S IO Ports Watchdog
Timer
Timer Compare / Capture Pulse
accumulator
READY
pin
Chip Selects Gatecount
HC05, HC08 DF6805 fast 64k + + - 4 + 1 2/2 - + - 7000
- DF6808 fast 64k + + - 4 + 1 2/2 - + - 8300
- D68HC05 legacy 64k + + + 4 + 1 1/1 - - - -
- D68HC08 legacy 64K + + + 4 + 1 2/1 - - - 10000
HC11 DF6811E fast 64k + + + 5 + 1 5/4 + + - 12000
- DF6811F fast 64k + + + 7 + 1 5/4 + + - 14000
- DF6811K fast 1M + + + 10 + 3 13/6 + + - 21000
- D68HC11E legacy 64k + + + 5 + 1 5/4 + - - 13000
- D68HC11K legacy 1M + + 1 10 + 3 13/6 + - 4 21000
- D68HC11F legacy 64k + + + 7 + 1 5/4 - - 4 13500
6802, 6803 DF6802 fast 64k + - - - - - - - - - -
- DF6803 fast 64k + + + 4 - 1 + - - - -
- D6802 legacy 64k + - - - - - - - - - 3600
- D6803 legacy 64k + + + 4 - 1 + - - - 6000

The main features of each D68XX and DF68XX family member, have been summarized in the table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and request the core modifications.

Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

Implementation Speed
grade
Utilized Area
[Slices]
Frequency
[MHz]
SPARTAN-III -7 793 46
SPARTAN-IIIE -5 793 47
SPARTAN-IIIA -5 880 57
VIRTEX-II -6 789 62
VIRTEX-IV -12 793 92

Implementation results of the DF6802 in XILINX devices. All features are included.

Implementation Speed
grade
Utilized Area
[LC]
Frequency
[MHz]
CYCLONE -6 1616 53
CYCLONE II -6 1619 58
CYCLONE III -6 1619 66
STRATIX -5 1687 51
STRATIX II -3 1095 98
STRATIX III -2 1093 137

DF6802 implementation results for ALTERA devices. All features have been included. 


CPU Features


Symbol

 clk
 rst
 cmf
 halt
 docddatai
 clkdocd
docddatao 
docdclk 
 irq
 nmi
 re
 mr
 iramdatai (7:0)
 xdatai (7:0)
ba 
vma 
iramoe 
iramwe 
xwe 
xoe 
addr (15:0) 
datao (7:0) 

Pins description

PinTypeDescription
clkinputGlobal clock
rstinputGlobal reset
cmfinputClock monitor fail reset
haltinputHalt clock system
docddataiinputDoCDTM serial data input
clkdocdinputClock signal to DoCDTM On chip Debugger module. This separate clock line allow DoCDTM to operate during the SLEEP mode (major clock CLK is stopped).
irqinputInterrupt input
nmiinputNon-maskable interrupt input
reinputInternal RAM enable input
mrinputMemory ready input
iramdatai (7:0)inputInternal Data memory bus input
xdatai (7:0)inputExternal memory bus input
docddataooutputDoCDTM serial data output
docdclkoutputDoCDTM serial data clock line
baoutputBus available output
vmaoutputValid memory address
iramoeoutputInternal Program / Data memory output enable
iramweoutputInternal Program / Data memory write enable
xweoutputExternal memory write enable
xoeoutputExternal memory output enable
addr (15:0)outputCommon address bus
datao (7:0)outputData bus output

Block Diagram

Opcode DecoderPerforms an opcode decoding instruction and control functions for all other blocks.
Control UnitPerforms the core synchronization and data flow control. This module manages execution of all instructions. The Control Unit also manages HALT input pin events.
halt
ALUArithmetic Logic Unit performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (A, B), Condition Code Register (CCREG), Index register X and related logic, like arithmetic unit, logic unit, multiplier and divider.
DoCDTM DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurs at particular address, with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
The separate DoCDTM clock line, allows debugger to operate in the SLEEP mode (major clock line CLK is stopped).
docddatai
docddatao
docdclk
clkdocd
Interrupt ControllerInterrupt Controller – Interrupt Control module is responsible for the interrupt manage system, for the processing of the external and internal interrupts and exceptions. It manages auto-vectored interrupt cycles, priority resolving and correct vector numbers creation.
irq
nmi
Bus ControllerProgram Memory, Data Memory interface controls access into the program and data memories. It contains Program Counter (PC), Stack Pointer (SP) register, and related logic.
re
mr
ba
vma
iramoe
iramwe
iramdatai (7:0)
xdatai (7:0)
xwe
xoe
addr (15:0)
datao (7:0)
clk
rst
cmf
Data bus Internal 8-bit data bus.

Units

Opcode Decoder
Performs an opcode decoding instruction and control functions for all other blocks.
Control Unit
Performs the core synchronization and data flow control. This module manages execution of all instructions. The Control Unit also manages HALT input pin events.
ALU
Arithmetic Logic Unit performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (A, B), Condition Code Register (CCREG), Index register X and related logic, like arithmetic unit, logic unit, multiplier and divider.

DoCDTM
DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurs at particular address, with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
The separate DoCDTM clock line, allows debugger to operate in the SLEEP mode (major clock line CLK is stopped).
Interrupt Controller
Interrupt Controller – Interrupt Control module is responsible for the interrupt manage system, for the processing of the external and internal interrupts and exceptions. It manages auto-vectored interrupt cycles, priority resolving and correct vector numbers creation.
Bus Controller
Program Memory, Data Memory interface controls access into the program and data memories. It contains Program Counter (PC), Stack Pointer (SP) register, and related logic.